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gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.043695 # Number of seconds simulated
sim_ticks 1043695084000 # Number of ticks simulated
final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 974812 # Simulator instruction rate (inst/s)
host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1591272225 # Simulator tick rate (ticks/s)
host_mem_usage 314196 # Number of bytes of host memory used
host_seconds 655.89 # Real time elapsed on the host
sim_insts 639366786 # Number of instructions simulated
sim_ops 785501034 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory
system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory
system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 223619 # Transaction distribution
system.membus.trans_dist::ReadResp 223619 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 355811 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 355811 # Request fanout histogram
system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 2087390168 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 639366786 # Number of instructions committed
system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
system.cpu.num_int_insts 682251400 # number of integer instructions
system.cpu.num_fp_insts 24239771 # number of float instructions
system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2087390168 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 137364859 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730743 # Class of executed instruction
system.cpu.icache.tags.replacements 8769 # number of replacements
system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits
system.cpu.icache.overall_hits::total 643367691 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
system.cpu.icache.overall_misses::total 10208 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 256932 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
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system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits::cpu.data 494200 # number of overall hits
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system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.writebacks::total 66098 # number of writebacks
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system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
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system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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