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gem5/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
Steve Reinhardt 13a15c55a4 stats: update stats for previous cset 
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 1338185 # Simulator instruction rate (inst/s)
host_mem_usage 196956 # Number of bytes of host memory used
host_seconds 447.34 # Real time elapsed on the host
host_tick_rate 1781116972 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated
sim_seconds 0.796760 # Number of seconds simulated
sim_ticks 796759936000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses
system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 216774877 # number of overall hits
system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses
system.cpu.dcache.overall_misses 437591 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 433495 # number of replacements
system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 392389 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 570070553 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 570069910 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 886578.398134 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 570070553 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.demand_hits 570069910 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context
system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 570069910 # number of overall hits
system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 643 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use
system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 348237 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 89997 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 71809 # number of replacements
system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1593519872 # number of cpu cycles simulated
system.cpu.num_insts 598619824 # Number of instructions executed
system.cpu.num_refs 219174038 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
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