gem5/cpu/beta_cpu/rob.cc at 04745696b6b523c5e90c335298099600d4a14a76 - sanchayanmaity/gem5 - Sanchayan Maity's repositories

sanchayanmaity/gem5

Kevin Lim 04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.

SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519

2004-08-20 14:54:07 -04:00

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 #include "cpu/beta_cpu/alpha_dyn_inst.hh"
 #include "cpu/beta_cpu/alpha_impl.hh"
 #include "cpu/beta_cpu/rob_impl.hh"
 // Force instantiation of InstructionQueue.
 template ROB<AlphaSimpleImpl>;