04745696b6
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
443 lines
15 KiB
C++
443 lines
15 KiB
C++
// @todo: Fix the instantaneous communication among all the stages within
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// iew. There's a clear delay between issue and execute, yet backwards
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// communication happens simultaneously. Might not be that bad really...
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// it might skew stats a bit though. Issue would otherwise try to issue
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// instructions that would never be executed if there were a delay; without
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// it issue will simply squash. Make this stage block properly. Make this
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// stage delay after a squash properly. Update the statuses for each stage.
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// Actually read instructions out of the skid buffer.
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#include <queue>
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#include "base/timebuf.hh"
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#include "cpu/beta_cpu/iew.hh"
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template<class Impl, class IQ>
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SimpleIEW<Impl, IQ>::SimpleIEW(Params ¶ms)
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: // Just make this time buffer really big for now
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issueToExecQueue(20, 20),
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instQueue(params),
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commitToIEWDelay(params.commitToIEWDelay),
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renameToIEWDelay(params.renameToIEWDelay),
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issueToExecuteDelay(params.issueToExecuteDelay),
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issueReadWidth(params.issueWidth),
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issueWidth(params.issueWidth),
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executeWidth(params.executeWidth)
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{
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DPRINTF(IEW, "IEW: executeIntWidth: %i.\n", params.executeIntWidth);
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_status = Idle;
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_issueStatus = Idle;
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_exeStatus = Idle;
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_wbStatus = Idle;
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// Setup wire to read instructions coming from issue.
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fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
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// Instruction queue needs the queue between issue and execute.
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instQueue.setIssueToExecuteQueue(&issueToExecQueue);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::setCPU(FullCPU *cpu_ptr)
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{
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DPRINTF(IEW, "IEW: Setting CPU pointer.\n");
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cpu = cpu_ptr;
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instQueue.setCPU(cpu_ptr);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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DPRINTF(IEW, "IEW: Setting time buffer pointer.\n");
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timeBuffer = tb_ptr;
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// Setup wire to read information from time buffer, from commit.
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fromCommit = timeBuffer->getWire(-commitToIEWDelay);
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// Setup wire to write information back to previous stages.
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toRename = timeBuffer->getWire(0);
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// Instruction queue also needs main time buffer.
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instQueue.setTimeBuffer(tb_ptr);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
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{
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DPRINTF(IEW, "IEW: Setting rename queue pointer.\n");
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renameQueue = rq_ptr;
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// Setup wire to read information from rename queue.
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fromRename = renameQueue->getWire(-renameToIEWDelay);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
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{
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DPRINTF(IEW, "IEW: Setting IEW queue pointer.\n");
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iewQueue = iq_ptr;
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// Setup wire to write instructions to commit.
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toCommit = iewQueue->getWire(0);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::setRenameMap(RenameMap *rm_ptr)
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{
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DPRINTF(IEW, "IEW: Setting rename map pointer.\n");
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renameMap = rm_ptr;
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::wakeDependents(DynInst *inst)
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{
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instQueue.wakeDependents(inst);
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::block()
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{
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DPRINTF(IEW, "IEW: Blocking.\n");
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// Set the status to Blocked.
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_status = Blocked;
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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skidBuffer.push(*fromRename);
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// Note that this stage only signals previous stages to stall when
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// it is the cause of the stall originates at this stage. Otherwise
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// the previous stages are expected to check all possible stall signals.
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}
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template<class Impl, class IQ>
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inline void
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SimpleIEW<Impl, IQ>::unblock()
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{
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// Check if there's information in the skid buffer. If there is, then
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// set status to unblocking, otherwise set it directly to running.
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DPRINTF(IEW, "IEW: Reading instructions out of the skid "
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"buffer.\n");
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// Remove the now processed instructions from the skid buffer.
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skidBuffer.pop();
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// If there's still information in the skid buffer, then
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// continue to tell previous stages to stall. They will be
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// able to restart once the skid buffer is empty.
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if (!skidBuffer.empty()) {
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toRename->iewInfo.stall = true;
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} else {
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DPRINTF(IEW, "IEW: Stage is done unblocking.\n");
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_status = Running;
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}
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::squash()
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{
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DPRINTF(IEW, "IEW: Squashing all instructions.\n");
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_status = Squashing;
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// Tell the IQ to start squashing.
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instQueue.squash();
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// Tell rename to squash through the time buffer.
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// This communication may be redundant depending upon where squash()
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// is called.
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// toRename->iewInfo.squash = true;
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::squash(DynInst *inst)
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{
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DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC:%#x.\n",
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inst->PC);
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// Perhaps leave the squashing up to the ROB stage to tell it when to
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// squash?
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_status = Squashing;
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// Tell rename to squash through the time buffer.
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toRename->iewInfo.squash = true;
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// Also send PC update information back to prior stages.
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toRename->iewInfo.squashedSeqNum = inst->seqNum;
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toRename->iewInfo.nextPC = inst->readCalcTarg();
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toRename->iewInfo.predIncorrect = true;
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::tick()
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{
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// Considering putting all the state-determining stuff in this section.
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// Try to fill up issue queue with as many instructions as bandwidth
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// allows.
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// Decode should try to execute as many instructions as its bandwidth
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// will allow, as long as it is not currently blocked.
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// Check if the stage is in a running status.
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if (_status != Blocked && _status != Squashing) {
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DPRINTF(IEW, "IEW: Status is not blocked, attempting to run "
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"stage.\n");
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iew();
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// If it's currently unblocking, check to see if it should switch
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// to running.
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if (_status == Unblocking) {
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unblock();
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}
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} else if (_status == Squashing) {
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DPRINTF(IEW, "IEW: Still squashing.\n");
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// Check if stage should remain squashing. Stop squashing if the
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// squash signal clears.
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if (!fromCommit->commitInfo.squash &&
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!fromCommit->commitInfo.robSquashing) {
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DPRINTF(IEW, "IEW: Done squashing, changing status to "
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"running.\n");
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_status = Running;
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instQueue.stopSquash();
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} else {
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instQueue.doSquash();
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}
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// Also should advance its own time buffers if the stage ran.
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// Not sure about this...
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// issueToExecQueue.advance();
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} else if (_status == Blocked) {
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// Continue to tell previous stage to stall.
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toRename->iewInfo.stall = true;
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// Check if possible stall conditions have cleared.
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if (!fromCommit->commitInfo.stall &&
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!instQueue.isFull()) {
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DPRINTF(IEW, "IEW: Stall signals cleared, going to unblock.\n");
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_status = Unblocking;
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}
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// If there's still instructions coming from rename, continue to
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// put them on the skid buffer.
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if (fromRename->insts[0] != NULL) {
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block();
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}
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if (fromCommit->commitInfo.squash ||
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fromCommit->commitInfo.robSquashing) {
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squash();
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}
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}
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// @todo: Maybe put these at the beginning, so if it's idle it can
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// return early.
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// Write back number of free IQ entries here.
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toRename->iewInfo.freeIQEntries = instQueue.numFreeEntries();
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DPRINTF(IEW, "IEW: IQ has %i free entries.\n",
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instQueue.numFreeEntries());
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}
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template<class Impl, class IQ>
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void
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SimpleIEW<Impl, IQ>::iew()
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{
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// Might want to put all state checks in the tick() function.
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// Check if being told to stall from commit.
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if (fromCommit->commitInfo.stall) {
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block();
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return;
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} else if (fromCommit->commitInfo.squash ||
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fromCommit->commitInfo.robSquashing) {
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// Also check if commit is telling this stage to squash.
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squash();
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return;
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}
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////////////////////////////////////////
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//ISSUE stage
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////////////////////////////////////////
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//Put into its own function?
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//Add instructions to IQ if there are any instructions there
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// Check if there are any instructions coming from rename, and we're.
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// not squashing.
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if (fromRename->insts[0] != NULL && _status != Squashing) {
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// Loop through the instructions, putting them in the instruction
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// queue.
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for (int inst_num = 0; inst_num < issueReadWidth; ++inst_num)
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{
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DynInst *inst = fromRename->insts[inst_num];
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// Make sure there's a valid instruction there.
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if (inst == NULL)
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break;
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DPRINTF(IEW, "IEW: Issue: Adding PC %#x to IQ.\n",
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inst->readPC());
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// If it's a memory reference, don't put it in the
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// instruction queue. These will only be executed at commit.
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// Do the same for nonspeculative instructions and nops.
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// Be sure to mark these instructions as ready so that the
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// commit stage can go ahead and execute them, and mark
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// them as issued so the IQ doesn't reprocess them.
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if (inst->isMemRef()) {
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DPRINTF(IEW, "IEW: Issue: Memory instruction "
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"encountered, skipping.\n");
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inst->setIssued();
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inst->setExecuted();
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inst->setCanCommit();
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instQueue.advanceTail(inst);
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continue;
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} else if (inst->isNonSpeculative()) {
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DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction "
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"encountered, skipping.\n");
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inst->setIssued();
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inst->setExecuted();
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inst->setCanCommit();
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instQueue.advanceTail(inst);
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continue;
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} else if (inst->isNop()) {
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DPRINTF(IEW, "IEW: Issue: Nop instruction encountered "
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", skipping.\n");
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inst->setIssued();
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inst->setExecuted();
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inst->setCanCommit();
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instQueue.advanceTail(inst);
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continue;
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} else if (instQueue.isFull()) {
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DPRINTF(IEW, "IEW: Issue: IQ has become full.\n");
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// Call function to start blocking.
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block();
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// Tell previous stage to stall.
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toRename->iewInfo.stall = true;
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break;
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}
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// If the instruction queue is not full, then add the
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// instruction.
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instQueue.insert(fromRename->insts[inst_num]);
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}
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}
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// Have the instruction queue try to schedule any ready instructions.
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instQueue.scheduleReadyInsts();
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////////////////////////////////////////
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//EXECUTE/WRITEBACK stage
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////////////////////////////////////////
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//Put into its own function?
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//Similarly should probably have separate execution for int vs FP.
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// Above comment is handled by the issue queue only issuing a valid
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// mix of int/fp instructions.
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//Actually okay to just have one execution, buuuuuut will need
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//somewhere that defines the execution latency of all instructions.
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// @todo: Move to the FU pool used in the current full cpu.
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int fu_usage = 0;
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// Execute/writeback any instructions that are available.
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for (int inst_num = 0;
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fu_usage < executeWidth && /* Haven't exceeded available FU's. */
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inst_num < issueWidth && /* Haven't exceeded issue width. */
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fromIssue->insts[inst_num]; /* There are available instructions. */
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++inst_num) {
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DPRINTF(IEW, "IEW: Execute: Executing instructions from IQ.\n");
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// Get instruction from issue's queue.
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DynInst *inst = fromIssue->insts[inst_num];
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DPRINTF(IEW, "IEW: Execute: Processing PC %#x.\n", inst->readPC());
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inst->setExecuted();
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// Check if the instruction is squashed; if so then skip it
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// and don't count it towards the FU usage.
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if (inst->isSquashed()) {
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DPRINTF(IEW, "IEW: Execute: Instruction was squashed.\n");
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continue;
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}
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// If an instruction is executed, then count it towards FU usage.
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++fu_usage;
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// Execute instruction.
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// Note that if the instruction faults, it will be handled
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// at the commit stage.
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inst->execute();
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// First check the time slot that this instruction will write
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// to. If there are free write ports at the time, then go ahead
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// and write the instruction to that time. If there are not,
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// keep looking back to see where's the first time there's a
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// free slot. What happens if you run out of free spaces?
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// For now naively assume that all instructions take one cycle.
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// Otherwise would have to look into the time buffer based on the
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// latency of the instruction.
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// Add finished instruction to queue to commit.
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toCommit->insts[inst_num] = inst;
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// Check if branch was correct. This check happens after the
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// instruction is added to the queue because even if the branch
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// is mispredicted, the branch instruction itself is still valid.
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if (inst->mispredicted()) {
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DPRINTF(IEW, "IEW: Execute: Branch mispredict detected.\n");
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DPRINTF(IEW, "IEW: Execute: Redirecting fetch to PC: %#x.\n",
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inst->nextPC);
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// If incorrect, then signal the ROB that it must be squashed.
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squash(inst);
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// Not sure it really needs to break.
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// break;
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}
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}
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// Loop through the head of the time buffer and wake any dependents.
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// These instructions are about to write back. In the simple model
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// this loop can really happen within the previous loop, but when
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// instructions have actual latencies, this loop must be separate.
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// Also mark scoreboard that this instruction is finally complete.
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// Either have IEW have direct access to rename map, or have this as
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// part of backwards communication.
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for (int inst_num = 0; inst_num < executeWidth &&
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toCommit->insts[inst_num] != NULL; inst_num++)
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{
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DynInst *inst = toCommit->insts[inst_num];
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DPRINTF(IEW, "IEW: Sending instructions to commit, PC %#x.\n",
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inst->readPC());
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instQueue.wakeDependents(inst);
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for (int i = 0; i < inst->numDestRegs(); i++)
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{
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renameMap->markAsReady(inst->renamedDestRegIdx(i));
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}
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}
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// Also should advance its own time buffers if the stage ran.
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// Not the best place for it, but this works (hopefully).
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issueToExecQueue.advance();
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}
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