SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
161 lines
4.1 KiB
C++
161 lines
4.1 KiB
C++
// Todo: add in statistics, only get the MachInst and let decode actually
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// decode, think about SMT fetch,
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// fix up branch prediction stuff into one thing,
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// Figure out where to advance time buffer. Add a way to get a
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// stage's current status.
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#ifndef __SIMPLE_FETCH_HH__
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#define __SIMPLE_FETCH_HH__
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//Will want to include: time buffer, structs, MemInterface, Event,
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//whatever class bzero uses, MemReqPtr
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#include "base/timebuf.hh"
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#include "sim/eventq.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/beta_cpu/comm.hh"
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#include "mem/mem_interface.hh"
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using namespace std;
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/**
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* SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
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* will stall if there's an Icache miss, but otherwise assumes a one cycle
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* Icache hit. This will be replaced with a more fleshed out class in the
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* future.
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*/
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template <class Impl>
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class SimpleFetch
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{
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public:
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/** Typedefs from Impl. */
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typedef typename Impl::ISA ISA;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::Params Params;
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typedef typename Impl::FetchStruct FetchStruct;
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typedef typename Impl::TimeStruct TimeStruct;
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/** Typedefs from ISA. */
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typedef typename ISA::MachInst MachInst;
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public:
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enum Status {
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Running,
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Idle,
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Squashing,
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Blocked,
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IcacheMissStall,
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IcacheMissComplete
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};
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// May eventually need statuses on a per thread basis.
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Status _status;
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bool stalled;
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public:
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/** SimpleFetch constructor. */
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SimpleFetch(Params ¶ms);
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void setCPU(FullCPU *cpu_ptr);
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void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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void tick();
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void fetch();
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void processCacheCompletion();
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// private:
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// Figure out PC vs next PC and how it should be updated
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void squash(Addr newPC);
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public:
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class CacheCompletionEvent : public Event
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{
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private:
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SimpleFetch *fetch;
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public:
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CacheCompletionEvent(SimpleFetch *_fetch);
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virtual void process();
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virtual const char *description();
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};
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CacheCompletionEvent cacheCompletionEvent;
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private:
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/** Pointer to the FullCPU. */
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FullCPU *cpu;
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get decode's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromDecode;
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/** Wire to get rename's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromRename;
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/** Wire to get iew's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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// Will probably have this sit in the FullCPU and just pass a pointr in.
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// Simplifies the constructors of all stages.
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/** Internal fetch instruction queue. */
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TimeBuffer<FetchStruct> *fetchQueue;
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//Might be annoying how this name is different than the queue.
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/** Wire used to write any information heading to decode. */
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typename TimeBuffer<FetchStruct>::wire toDecode;
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/** Icache interface. */
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MemInterface *icacheInterface;
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/** Memory request used to access cache. */
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MemReqPtr memReq;
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/** Decode to fetch delay, in ticks. */
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unsigned decodeToFetchDelay;
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/** Rename to fetch delay, in ticks. */
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unsigned renameToFetchDelay;
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/** IEW to fetch delay, in ticks. */
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unsigned iewToFetchDelay;
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/** Commit to fetch delay, in ticks. */
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unsigned commitToFetchDelay;
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/** The width of fetch in instructions. */
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unsigned fetchWidth;
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/** Cache block size. */
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int blkSize;
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/** Mask to get a cache block's address. */
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Addr cacheBlockMask;
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/** The instruction being fetched. */
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MachInst inst;
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/** Size of instructions. */
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int instSize;
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/** Icache stall statistics. */
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// Stats::Scalar<> icacheStallCycles;
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// Counter lastIcacheStall;
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};
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#endif //__SIMPLE_FETCH_HH__
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