04745696b6
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
150 lines
4.3 KiB
C++
150 lines
4.3 KiB
C++
// Todo: Squash properly. Have commit be able to send a squash signal
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// to previous stages; will be needed when trap() is implemented.
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// Maybe have a special method for handling interrupts/traps.
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//
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// Traps: Have IEW send a signal to commit saying that there's a trap to
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// be handled. Have commit send the PC back to the fetch stage, along
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// with the current commit PC. Fetch will directly access the IPR and save
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// off all the proper stuff. Commit can send out a squash, or something
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// close to it.
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// Do the same for hwrei(). However, requires that commit be specifically
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// built to support that kind of stuff. Probably not horrible to have
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// commit support having the CPU tell it to squash the other stages and
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// restart at a given address. The IPR register does become an issue.
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// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
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// have the original function handle writing to the IPR register.
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#ifndef __SIMPLE_COMMIT_HH__
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#define __SIMPLE_COMMIT_HH__
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//Includes: ROB, time buffer, structs, memory interface
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#include "arch/alpha/isa_traits.hh"
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#include "base/timebuf.hh"
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#include "cpu/beta_cpu/comm.hh"
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#include "cpu/beta_cpu/rename_map.hh"
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#include "cpu/beta_cpu/rob.hh"
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#include "mem/memory_interface.hh"
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template<class Impl>
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class SimpleCommit
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{
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public:
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// Typedefs from the Impl.
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typedef typename Impl::ISA ISA;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::Params Params;
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typedef typename Impl::CPUPol::ROB ROB;
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typedef typename Impl::TimeStruct TimeStruct;
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typedef typename Impl::IEWStruct IEWStruct;
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typedef typename Impl::RenameStruct RenameStruct;
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public:
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// I don't believe commit can block, so it will only have two
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// statuses for now.
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// Actually if there's a cache access that needs to block (ie
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// uncachable load or just a mem access in commit) then the stage
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// may have to wait.
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enum Status {
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Running,
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Idle,
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ROBSquashing,
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DcacheMissStall,
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DcacheMissComplete
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};
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private:
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Status _status;
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public:
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SimpleCommit(Params ¶ms);
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void setCPU(FullCPU *cpu_ptr);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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void setROB(ROB *rob_ptr);
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void tick();
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void commit();
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uint64_t readCommitPC();
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void setSquashing() { _status = ROBSquashing; }
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private:
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void commitInsts();
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bool commitHead(DynInst *head_inst, unsigned inst_num);
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void getInsts();
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void markCompletedInsts();
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toIEW;
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/** Wire to read information from IEW (for ROB). */
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typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
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/** IEW instruction queue interface. */
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to read information from IEW queue. */
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typename TimeBuffer<IEWStruct>::wire fromIEW;
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/** Rename instruction queue interface, for ROB. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to read information from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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/** ROB interface. */
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ROB *rob;
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/** Pointer to FullCPU. */
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FullCPU *cpu;
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/** Pointer to the rename map. DO NOT USE if possible. */
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typename Impl::CPUPol::RenameMap *renameMap;
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//Store buffer interface? Will need to move committed stores to the
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//store buffer
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/** Memory interface. Used for d-cache accesses. */
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MemInterface *dcacheInterface;
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private:
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/** IEW to Commit delay, in ticks. */
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unsigned iewToCommitDelay;
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/** Rename to ROB delay, in ticks. */
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unsigned renameToROBDelay;
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/** Rename width, in instructions. Used so ROB knows how many
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* instructions to get from the rename instruction queue.
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*/
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unsigned renameWidth;
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/** IEW width, in instructions. Used so ROB knows how many
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* instructions to get from the IEW instruction queue.
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*/
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unsigned iewWidth;
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/** Commit width, in instructions. */
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unsigned commitWidth;
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};
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#endif // __SIMPLE_COMMIT_HH__
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