04745696b6
SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
85 lines
1.8 KiB
C++
85 lines
1.8 KiB
C++
#ifndef __ALPHA_SIMPLE_PARAMS_HH__
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#define __ALPHA_SIMPLE_PARAMS_HH__
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//Forward declarations
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class System;
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class AlphaITB;
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class AlphaDTB;
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class FunctionalMemory;
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class Process;
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class MemInterface;
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/**
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* This file defines the parameters that will be used for the AlphaFullCPU.
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* This must be defined externally so that the Impl can have a params class
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* defined that it can pass to all of the individual stages.
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*/
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class AlphaSimpleParams
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{
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public:
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std::string name;
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int numberOfThreads;
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#ifdef FULL_SYSTEM
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System *_system;
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AlphaITB *itb; AlphaDTB *dtb;
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Tick freq;
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#else
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std::vector<Process *> workload;
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Process *process;
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short asid;
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#endif // FULL_SYSTEM
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FunctionalMemory *mem;
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Counter maxInstsAnyThread;
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Counter maxInstsAllThreads;
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Counter maxLoadsAnyThread;
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Counter maxLoadsAllThreads;
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//
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// Caches
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//
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MemInterface *icacheInterface;
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MemInterface *dcacheInterface;
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unsigned decodeToFetchDelay;
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unsigned renameToFetchDelay;
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unsigned iewToFetchDelay;
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unsigned commitToFetchDelay;
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unsigned fetchWidth;
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unsigned renameToDecodeDelay;
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unsigned iewToDecodeDelay;
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unsigned commitToDecodeDelay;
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unsigned fetchToDecodeDelay;
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unsigned decodeWidth;
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unsigned iewToRenameDelay;
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unsigned commitToRenameDelay;
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unsigned decodeToRenameDelay;
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unsigned renameWidth;
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unsigned commitToIEWDelay;
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unsigned renameToIEWDelay;
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unsigned issueToExecuteDelay;
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unsigned issueWidth;
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unsigned executeWidth;
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unsigned executeIntWidth;
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unsigned executeFloatWidth;
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unsigned iewToCommitDelay;
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unsigned renameToROBDelay;
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unsigned commitWidth;
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unsigned squashWidth;
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unsigned numPhysIntRegs;
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unsigned numPhysFloatRegs;
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unsigned numIQEntries;
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unsigned numROBEntries;
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bool defReg;
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};
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#endif
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