gem5/cpu/beta_cpu/alpha_params.hh
Kevin Lim 04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
2004-08-20 14:54:07 -04:00

85 lines
1.8 KiB
C++

#ifndef __ALPHA_SIMPLE_PARAMS_HH__
#define __ALPHA_SIMPLE_PARAMS_HH__
//Forward declarations
class System;
class AlphaITB;
class AlphaDTB;
class FunctionalMemory;
class Process;
class MemInterface;
/**
* This file defines the parameters that will be used for the AlphaFullCPU.
* This must be defined externally so that the Impl can have a params class
* defined that it can pass to all of the individual stages.
*/
class AlphaSimpleParams
{
public:
std::string name;
int numberOfThreads;
#ifdef FULL_SYSTEM
System *_system;
AlphaITB *itb; AlphaDTB *dtb;
Tick freq;
#else
std::vector<Process *> workload;
Process *process;
short asid;
#endif // FULL_SYSTEM
FunctionalMemory *mem;
Counter maxInstsAnyThread;
Counter maxInstsAllThreads;
Counter maxLoadsAnyThread;
Counter maxLoadsAllThreads;
//
// Caches
//
MemInterface *icacheInterface;
MemInterface *dcacheInterface;
unsigned decodeToFetchDelay;
unsigned renameToFetchDelay;
unsigned iewToFetchDelay;
unsigned commitToFetchDelay;
unsigned fetchWidth;
unsigned renameToDecodeDelay;
unsigned iewToDecodeDelay;
unsigned commitToDecodeDelay;
unsigned fetchToDecodeDelay;
unsigned decodeWidth;
unsigned iewToRenameDelay;
unsigned commitToRenameDelay;
unsigned decodeToRenameDelay;
unsigned renameWidth;
unsigned commitToIEWDelay;
unsigned renameToIEWDelay;
unsigned issueToExecuteDelay;
unsigned issueWidth;
unsigned executeWidth;
unsigned executeIntWidth;
unsigned executeFloatWidth;
unsigned iewToCommitDelay;
unsigned renameToROBDelay;
unsigned commitWidth;
unsigned squashWidth;
unsigned numPhysIntRegs;
unsigned numPhysFloatRegs;
unsigned numIQEntries;
unsigned numROBEntries;
bool defReg;
};
#endif