04745696b6
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
911 lines
25 KiB
C++
911 lines
25 KiB
C++
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/full_cpu/dd_queue.hh"
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#include "cpu/full_cpu/full_cpu.hh"
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#include "cpu/full_cpu/rob_station.hh"
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#include "mem/cache/cache.hh" // for dynamic cast
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/beta_cpu/alpha_full_cpu.hh"
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#include "cpu/beta_cpu/alpha_params.hh"
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#include "cpu/beta_cpu/comm.hh"
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AlphaFullCPU::AlphaFullCPU(Params ¶ms)
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: FullBetaCPU<AlphaSimpleImpl>(params)
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{
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fetch.setCPU(this);
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decode.setCPU(this);
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rename.setCPU(this);
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iew.setCPU(this);
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commit.setCPU(this);
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rob.setCPU(this);
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}
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#ifndef FULL_SYSTEM
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void
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AlphaFullCPU::syscall()
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
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squashStages();
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// Copy over all important state to xc once all the unrolling is done.
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copyToXC();
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process->syscall(xc);
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// Copy over all important state back to normal.
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copyFromXC();
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}
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// This is not a pretty function, and should only be used if it is necessary
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// to fake having everything squash all at once (ie for non-full system
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// syscalls).
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void
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AlphaFullCPU::squashStages()
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{
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InstSeqNum rob_head = rob.readHeadSeqNum();
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// Now hack the time buffer to put this sequence number in the places
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// where the stages might read it.
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for (int i = 0; i < 10; ++i)
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{
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timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
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}
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fetch.squash(rob.readHeadNextPC());
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fetchQueue.advance();
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decode.squash();
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decodeQueue.advance();
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rename.squash();
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renameQueue.advance();
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renameQueue.advance();
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iew.squash();
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iewQueue.advance();
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iewQueue.advance();
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rob.squash(rob_head);
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commit.setSquashing();
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}
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#endif // FULL_SYSTEM
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void
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AlphaFullCPU::copyToXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i);
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xc->regs.intRegFile[i] = regFile.intRegFile[renamed_reg];
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DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
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renamed_reg, regFile.intRegFile[renamed_reg]);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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xc->regs.floatRegFile.d[i] = regFile.floatRegFile[renamed_reg].d;
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xc->regs.floatRegFile.q[i] = regFile.floatRegFile[renamed_reg].q;
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}
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xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr;
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xc->regs.miscRegs.uniq = regFile.miscRegs.uniq;
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xc->regs.miscRegs.lock_flag = regFile.miscRegs.lock_flag;
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xc->regs.miscRegs.lock_addr = regFile.miscRegs.lock_addr;
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xc->regs.pc = rob.readHeadPC();
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xc->regs.npc = xc->regs.pc+4;
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xc->func_exe_inst = funcExeInst;
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}
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// This function will probably mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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void
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AlphaFullCPU::copyFromXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i);
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DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
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"now has data %lli.\n",
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renamed_reg, regFile.intRegFile[renamed_reg],
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xc->regs.intRegFile[i]);
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regFile.intRegFile[renamed_reg] = xc->regs.intRegFile[i];
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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regFile.floatRegFile[renamed_reg].d = xc->regs.floatRegFile.d[i];
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regFile.floatRegFile[renamed_reg].q = xc->regs.floatRegFile.q[i] ;
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}
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// Then loop through the misc registers.
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regFile.miscRegs.fpcr = xc->regs.miscRegs.fpcr;
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regFile.miscRegs.uniq = xc->regs.miscRegs.uniq;
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regFile.miscRegs.lock_flag = xc->regs.miscRegs.lock_flag;
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regFile.miscRegs.lock_addr = xc->regs.miscRegs.lock_addr;
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// Then finally set the PC and the next PC.
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// regFile.pc = xc->regs.pc;
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// regFile.npc = xc->regs.npc;
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funcExeInst = xc->func_exe_inst;
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}
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#ifdef FULL_SYSTEM
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uint64_t *
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AlphaFullCPU::getIpr()
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{
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return regs.ipr;
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}
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uint64_t
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AlphaFullCPU::readIpr(int idx, Fault &fault)
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{
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uint64_t *ipr = getIpr();
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= curTick & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = dtb->index(!misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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fault = Unimplemented_Opcode_Fault;
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break;
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default:
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// invalid IPR
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fault = Unimplemented_Opcode_Fault;
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break;
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}
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return retval;
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}
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Fault
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AlphaFullCPU::setIpr(int idx, uint64_t val)
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{
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uint64_t *ipr = getIpr();
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uint64_t old;
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if (misspeculating())
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return No_Fault;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case AlphaISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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kernelStats.context(old, val);
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break;
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case AlphaISA::IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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break;
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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// only write least significant four bits - privilege mask
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ipr[idx] = val & 0xf;
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break;
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case AlphaISA::IPR_IPLR:
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#ifdef DEBUG
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if (break_ipl != -1 && break_ipl == (val & 0x1f))
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debug_break();
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#endif
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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kernelStats.swpipl(ipr[idx]);
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break;
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case AlphaISA::IPR_DTB_CM:
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kernelStats.mode((val & 0x18) != 0);
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case AlphaISA::IPR_ICM:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_ALT_MODE:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_MCSR:
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// more here after optimization...
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_SIRR:
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// only write software interrupt mask
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ipr[idx] = val & 0x7fff0;
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break;
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case AlphaISA::IPR_ICSR:
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ipr[idx] = val & ULL(0xffffff0300);
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break;
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_MVPTBR:
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ipr[idx] = val & ULL(0xffffffffc0000000);
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break;
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case AlphaISA::IPR_DC_TEST_CTL:
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ipr[idx] = val & 0x1ffb;
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break;
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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ipr[idx] = val & 0x3f;
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break;
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case AlphaISA::IPR_ITB_ASN:
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ipr[idx] = val & 0x7f0;
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break;
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case AlphaISA::IPR_DTB_ASN:
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ipr[idx] = val & ULL(0xfe00000000000000);
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break;
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case AlphaISA::IPR_EXC_SUM:
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case AlphaISA::IPR_EXC_MASK:
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// any write to this register clears it
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ipr[idx] = 0;
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break;
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_SL_RCV:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_ITB_PTE_TEMP:
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case AlphaISA::IPR_DTB_PTE_TEMP:
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// read-only registers
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return Unimplemented_Opcode_Fault;
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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// the following are write only
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_DTB_IA:
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// really a control write
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ipr[idx] = 0;
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dtb->flushAll();
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break;
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case AlphaISA::IPR_DTB_IAP:
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// really a control write
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ipr[idx] = 0;
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dtb->flushProcesses();
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break;
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case AlphaISA::IPR_DTB_IS:
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// really a control write
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ipr[idx] = val;
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dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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break;
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case AlphaISA::IPR_DTB_TAG: {
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struct AlphaISA::PTE pte;
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// FIXME: granularity hints NYI...
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if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
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panic("PTE GH field != 0");
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// write entire quad
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ipr[idx] = val;
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// construct PTE for new entry
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pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
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// insert new TAG/PTE value into data TLB
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dtb->insert(val, pte);
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}
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break;
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case AlphaISA::IPR_ITB_PTE: {
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struct AlphaISA::PTE pte;
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// FIXME: granularity hints NYI...
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if (ITB_PTE_GH(val) != 0)
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panic("PTE GH field != 0");
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// write entire quad
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ipr[idx] = val;
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// construct PTE for new entry
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pte.ppn = ITB_PTE_PPN(val);
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pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return Unimplemented_Opcode_Fault;
|
|
}
|
|
|
|
// no error...
|
|
return No_Fault;
|
|
|
|
}
|
|
|
|
int
|
|
AlphaFullCPU::readIntrFlag()
|
|
{
|
|
return regs.intrflag;
|
|
}
|
|
|
|
void
|
|
AlphaFullCPU::setIntrFlag(int val)
|
|
{
|
|
regs.intrflag = val;
|
|
}
|
|
|
|
// Maybe have this send back from IEW stage to squash and update PC.
|
|
Fault
|
|
AlphaFullCPU::hwrei()
|
|
{
|
|
uint64_t *ipr = getIpr();
|
|
|
|
if (!PC_PAL(regs.pc))
|
|
return Unimplemented_Opcode_Fault;
|
|
|
|
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
|
|
|
|
if (!misspeculating()) {
|
|
kernelStats.hwrei();
|
|
|
|
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
|
|
AlphaISA::swap_palshadow(®s, false);
|
|
|
|
AlphaISA::check_interrupts = true;
|
|
}
|
|
|
|
// FIXME: XXX check for interrupts? XXX
|
|
return No_Fault;
|
|
}
|
|
|
|
bool
|
|
AlphaFullCPU::inPalMode()
|
|
{
|
|
return PC_PAL(readPC());
|
|
}
|
|
|
|
bool
|
|
AlphaFullCPU::simPalCheck(int palFunc)
|
|
{
|
|
kernelStats.callpal(palFunc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Probably shouldn't be able to switch to the trap handler as quickly as
|
|
// this. Also needs to get the exception restart address from the commit
|
|
// stage.
|
|
void
|
|
AlphaFullCPU::trap(Fault fault)
|
|
{
|
|
uint64_t PC = commit.readPC();
|
|
|
|
DPRINTF(Fault, "Fault %s\n", FaultName(fault));
|
|
Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
|
|
|
|
assert(!misspeculating());
|
|
kernelStats.fault(fault);
|
|
|
|
if (fault == Arithmetic_Fault)
|
|
panic("Arithmetic traps are unimplemented!");
|
|
|
|
AlphaISA::InternalProcReg *ipr = getIpr();
|
|
|
|
// exception restart address - Get the commit PC
|
|
if (fault != Interrupt_Fault || !PC_PAL(PC))
|
|
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
|
|
|
|
if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
|
|
fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
|
|
// traps... skip faulting instruction
|
|
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
|
|
}
|
|
|
|
if (!PC_PAL(PC))
|
|
AlphaISA::swap_palshadow(®s, true);
|
|
|
|
setPC( ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault] );
|
|
setNextPC(PC + sizeof(MachInst));
|
|
}
|
|
|
|
void
|
|
AlphaFullCPU::processInterrupts()
|
|
{
|
|
// Check for interrupts here. For now can copy the code that exists
|
|
// within isa_fullsys_traits.hh.
|
|
}
|
|
|
|
// swap_palshadow swaps in the values of the shadow registers and
|
|
// swaps them with the values of the physical registers that map to the
|
|
// same logical index.
|
|
void
|
|
AlphaFullCPU::swap_palshadow(RegFile *regs, bool use_shadow)
|
|
{
|
|
if (palShadowEnabled == use_shadow)
|
|
panic("swap_palshadow: wrong PAL shadow state");
|
|
|
|
palShadowEnabled = use_shadow;
|
|
|
|
// Will have to lookup in rename map to get physical registers, then
|
|
// swap.
|
|
for (int i = 0; i < AlphaISA::NumIntRegs; i++) {
|
|
if (reg_redir[i]) {
|
|
AlphaISA::IntReg temp = regs->intRegFile[i];
|
|
regs->intRegFile[i] = regs->palregs[i];
|
|
regs->palregs[i] = temp;
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaFullCPU)
|
|
|
|
Param<int> numThreads;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
SimObjectParam<System *> system;
|
|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
Param<int> mult;
|
|
#else
|
|
SimObjectVectorParam<Process *> workload;
|
|
SimObjectParam<Process *> process;
|
|
Param<short> asid;
|
|
#endif // FULL_SYSTEM
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
SimObjectParam<BaseCache *> icache;
|
|
SimObjectParam<BaseCache *> dcache;
|
|
|
|
Param<unsigned> decodeToFetchDelay;
|
|
Param<unsigned> renameToFetchDelay;
|
|
Param<unsigned> iewToFetchDelay;
|
|
Param<unsigned> commitToFetchDelay;
|
|
Param<unsigned> fetchWidth;
|
|
|
|
Param<unsigned> renameToDecodeDelay;
|
|
Param<unsigned> iewToDecodeDelay;
|
|
Param<unsigned> commitToDecodeDelay;
|
|
Param<unsigned> fetchToDecodeDelay;
|
|
Param<unsigned> decodeWidth;
|
|
|
|
Param<unsigned> iewToRenameDelay;
|
|
Param<unsigned> commitToRenameDelay;
|
|
Param<unsigned> decodeToRenameDelay;
|
|
Param<unsigned> renameWidth;
|
|
|
|
Param<unsigned> commitToIEWDelay;
|
|
Param<unsigned> renameToIEWDelay;
|
|
Param<unsigned> issueToExecuteDelay;
|
|
Param<unsigned> issueWidth;
|
|
Param<unsigned> executeWidth;
|
|
Param<unsigned> executeIntWidth;
|
|
Param<unsigned> executeFloatWidth;
|
|
|
|
Param<unsigned> iewToCommitDelay;
|
|
Param<unsigned> renameToROBDelay;
|
|
Param<unsigned> commitWidth;
|
|
Param<unsigned> squashWidth;
|
|
|
|
Param<unsigned> numPhysIntRegs;
|
|
Param<unsigned> numPhysFloatRegs;
|
|
Param<unsigned> numIQEntries;
|
|
Param<unsigned> numROBEntries;
|
|
|
|
Param<bool> defReg;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaFullCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaFullCPU)
|
|
|
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
|
|
|
#ifdef FULL_SYSTEM
|
|
INIT_PARAM(system, "System object"),
|
|
INIT_PARAM(itb, "Instruction translation buffer"),
|
|
INIT_PARAM(dtb, "Data translation buffer"),
|
|
INIT_PARAM_DFLT(mult, "System clock multiplier", 1),
|
|
#else
|
|
INIT_PARAM(workload, "Processes to run"),
|
|
INIT_PARAM_DFLT(process, "Process to run", NULL),
|
|
INIT_PARAM(asid, "Address space ID"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
|
|
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
|
"Terminate when any thread reaches this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
|
"Terminate when all threads have reached"
|
|
"this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
|
"Terminate when any thread reaches this load count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
|
"Terminate when all threads have reached this load"
|
|
"count",
|
|
0),
|
|
|
|
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
|
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
|
|
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
|
"delay"),
|
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
|
|
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
|
"delay"),
|
|
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
|
|
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
|
|
INIT_PARAM(decodeWidth, "Decode width"),
|
|
|
|
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
|
|
"delay"),
|
|
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
|
|
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
|
|
INIT_PARAM(renameWidth, "Rename width"),
|
|
|
|
INIT_PARAM(commitToIEWDelay, "Commit to "
|
|
"Issue/Execute/Writeback delay"),
|
|
INIT_PARAM(renameToIEWDelay, "Rename to "
|
|
"Issue/Execute/Writeback delay"),
|
|
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
|
|
"to the IEW stage)"),
|
|
INIT_PARAM(issueWidth, "Issue width"),
|
|
INIT_PARAM(executeWidth, "Execute width"),
|
|
INIT_PARAM(executeIntWidth, "Integer execute width"),
|
|
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
|
|
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
|
"delay"),
|
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
|
INIT_PARAM(commitWidth, "Commit width"),
|
|
INIT_PARAM(squashWidth, "Squash width"),
|
|
|
|
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
|
|
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
|
|
"registers"),
|
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
|
|
|
INIT_PARAM(defReg, "Defer registration")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaFullCPU)
|
|
|
|
CREATE_SIM_OBJECT(AlphaFullCPU)
|
|
{
|
|
AlphaFullCPU *cpu;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
if (mult != 1)
|
|
panic("Processor clock multiplier must be 1?\n");
|
|
|
|
// Full-system only supports a single thread for the moment.
|
|
int actual_num_threads = 1;
|
|
#else
|
|
// In non-full-system mode, we infer the number of threads from
|
|
// the workload if it's not explicitly specified.
|
|
int actual_num_threads =
|
|
numThreads.isValid() ? numThreads : workload.size();
|
|
|
|
if (workload.size() == 0) {
|
|
fatal("Must specify at least one workload!");
|
|
}
|
|
|
|
Process *actual_process;
|
|
|
|
if (process == NULL) {
|
|
actual_process = workload[0];
|
|
} else {
|
|
actual_process = process;
|
|
}
|
|
|
|
#endif
|
|
|
|
AlphaSimpleParams params;
|
|
|
|
params.name = getInstanceName();
|
|
params.numberOfThreads = actual_num_threads;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
params._system = system;
|
|
params.itb = itb;
|
|
params.dtb = dtb;
|
|
params.freq = ticksPerSecond * mult;
|
|
#else
|
|
params.workload = workload;
|
|
params.process = actual_process;
|
|
params.asid = asid;
|
|
#endif // FULL_SYSTEM
|
|
|
|
params.mem = mem;
|
|
|
|
params.maxInstsAnyThread = max_insts_any_thread;
|
|
params.maxInstsAllThreads = max_insts_all_threads;
|
|
params.maxLoadsAnyThread = max_loads_any_thread;
|
|
params.maxLoadsAllThreads = max_loads_all_threads;
|
|
|
|
//
|
|
// Caches
|
|
//
|
|
params.icacheInterface = icache ? icache->getInterface() : NULL;
|
|
params.dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
|
|
|
params.decodeToFetchDelay = decodeToFetchDelay;
|
|
params.renameToFetchDelay = renameToFetchDelay;
|
|
params.iewToFetchDelay = iewToFetchDelay;
|
|
params.commitToFetchDelay = commitToFetchDelay;
|
|
params.fetchWidth = fetchWidth;
|
|
|
|
params.renameToDecodeDelay = renameToDecodeDelay;
|
|
params.iewToDecodeDelay = iewToDecodeDelay;
|
|
params.commitToDecodeDelay = commitToDecodeDelay;
|
|
params.fetchToDecodeDelay = fetchToDecodeDelay;
|
|
params.decodeWidth = decodeWidth;
|
|
|
|
params.iewToRenameDelay = iewToRenameDelay;
|
|
params.commitToRenameDelay = commitToRenameDelay;
|
|
params.decodeToRenameDelay = decodeToRenameDelay;
|
|
params.renameWidth = renameWidth;
|
|
|
|
params.commitToIEWDelay = commitToIEWDelay;
|
|
params.renameToIEWDelay = renameToIEWDelay;
|
|
params.issueToExecuteDelay = issueToExecuteDelay;
|
|
params.issueWidth = issueWidth;
|
|
params.executeWidth = executeWidth;
|
|
params.executeIntWidth = executeIntWidth;
|
|
params.executeFloatWidth = executeFloatWidth;
|
|
|
|
params.iewToCommitDelay = iewToCommitDelay;
|
|
params.renameToROBDelay = renameToROBDelay;
|
|
params.commitWidth = commitWidth;
|
|
params.squashWidth = squashWidth;
|
|
|
|
params.numPhysIntRegs = numPhysIntRegs;
|
|
params.numPhysFloatRegs = numPhysFloatRegs;
|
|
params.numIQEntries = numIQEntries;
|
|
params.numROBEntries = numROBEntries;
|
|
|
|
params.defReg = defReg;
|
|
|
|
cpu = new AlphaFullCPU(params);
|
|
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaFullCPU", AlphaFullCPU)
|
|
|