04745696b6
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
102 lines
1.5 KiB
C++
102 lines
1.5 KiB
C++
#ifndef __ALPHA_DYN_INST_CC__
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#define __ALPHA_DYN_INST_CC__
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#include "cpu/beta_cpu/alpha_dyn_inst.hh"
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// Force instantiation of BaseDynInst
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template BaseDynInst<AlphaSimpleImpl>;
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AlphaDynInst::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
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InstSeqNum seq_num, FullCPU *cpu)
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: BaseDynInst<AlphaSimpleImpl>(inst, PC, Pred_PC, seq_num, cpu)
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{
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// Initialize these to illegal values.
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robIdx = -1;
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iqIdx = -1;
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}
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AlphaDynInst::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
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: BaseDynInst<AlphaSimpleImpl>(_staticInst)
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{
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}
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uint64_t
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AlphaDynInst::readUniq()
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{
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return cpu->readUniq();
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}
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void
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AlphaDynInst::setUniq(uint64_t val)
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{
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cpu->setUniq(val);
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}
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uint64_t
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AlphaDynInst::readFpcr()
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{
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return cpu->readFpcr();
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}
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void
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AlphaDynInst::setFpcr(uint64_t val)
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{
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cpu->setFpcr(val);
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}
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#ifdef FULL_SYSTEM
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uint64_t
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AlphaDynInst::readIpr(int idx, Fault &fault)
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{
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return cpu->readIpr(idx, fault);
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}
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Fault
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AlphaDynInst::setIpr(int idx, uint64_t val)
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{
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return cpu->setIpr(idx, val);
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}
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Fault
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AlphaDynInst::hwrei()
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{
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return cpu->hwrei();
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}
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int
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AlphaDynInst::readIntrFlag()
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{
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return cpu->readIntrFlag();
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}
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void
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AlphaDynInst::setIntrFlag(int val)
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{
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cpu->setIntrFlag(val);
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}
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bool
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AlphaDynInst::inPalMode()
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{
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return cpu->inPalMode();
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}
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void
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AlphaDynInst::trap(Fault fault)
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{
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cpu->trap(fault);
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}
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bool
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AlphaDynInst::simPalCheck(int palFunc)
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{
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return cpu->simPalCheck(palFunc);
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}
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#else
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void
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AlphaDynInst::syscall()
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{
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cpu->syscall();
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}
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#endif
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#endif // __ALPHA_DYN_INST_CC__
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