1244 lines
143 KiB
Text
1244 lines
143 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.233976 # Number of seconds simulated
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sim_ticks 233975583000 # Number of ticks simulated
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final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 134400 # Simulator instruction rate (inst/s)
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host_op_rate 145602 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 62240486 # Simulator tick rate (ticks/s)
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host_mem_usage 347620 # Number of bytes of host memory used
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host_seconds 3759.22 # Real time elapsed on the host
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sim_insts 505237724 # Number of instructions simulated
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sim_ops 547350945 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 423029 # Number of read requests accepted
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system.physmem.writeReqs 292085 # Number of write requests accepted
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system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 26587 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25566 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25266 # Per bank write bursts
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system.physmem.perBankRdBursts::3 32149 # Per bank write bursts
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system.physmem.perBankRdBursts::4 27127 # Per bank write bursts
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system.physmem.perBankRdBursts::5 28227 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25084 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24199 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25413 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25760 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25321 # Per bank write bursts
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system.physmem.perBankRdBursts::11 26053 # Per bank write bursts
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system.physmem.perBankRdBursts::12 27496 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25872 # Per bank write bursts
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system.physmem.perBankRdBursts::14 24848 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25683 # Per bank write bursts
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system.physmem.perBankWrBursts::0 18549 # Per bank write bursts
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system.physmem.perBankWrBursts::1 18359 # Per bank write bursts
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system.physmem.perBankWrBursts::2 17952 # Per bank write bursts
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system.physmem.perBankWrBursts::3 17851 # Per bank write bursts
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system.physmem.perBankWrBursts::4 18559 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18328 # Per bank write bursts
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system.physmem.perBankWrBursts::6 17864 # Per bank write bursts
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system.physmem.perBankWrBursts::7 17725 # Per bank write bursts
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system.physmem.perBankWrBursts::8 17897 # Per bank write bursts
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system.physmem.perBankWrBursts::9 17869 # Per bank write bursts
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system.physmem.perBankWrBursts::10 18218 # Per bank write bursts
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system.physmem.perBankWrBursts::11 18760 # Per bank write bursts
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system.physmem.perBankWrBursts::12 18894 # Per bank write bursts
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system.physmem.perBankWrBursts::13 18283 # Per bank write bursts
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system.physmem.perBankWrBursts::14 18348 # Per bank write bursts
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system.physmem.perBankWrBursts::15 18588 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 233975530500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 423029 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 292085 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads
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system.physmem.totQLat 8699002486 # Total ticks spent queuing
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system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.52 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 305767 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 85381 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 327186.34 # Average gap between requests
|
|
system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 727.650714 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 726.084666 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 175127231 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 467951167 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued
|
|
system.cpu.iq.rate 1.304102 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1487698 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 131373584 # Number of branches executed
|
|
system.cpu.iew.exec_stores 60956693 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.280903 # Inst execution rate
|
|
system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 349898988 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581608 # Number of instructions committed
|
|
system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 172745233 # Number of memory references committed
|
|
system.cpu.commit.loads 115884756 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548302 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1095077893 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1334621527 # The number of ROB writes
|
|
system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237724 # Number of Instructions Simulated
|
|
system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 611089761 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 328120494 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2820720 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 166376823 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7358653 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2820720 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2820720 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542826 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2542826 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994565 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1994565 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2301669 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519581 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 519581 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 34151609494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34152313994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 34152313994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12838.994660 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12838.994660 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8854.237345 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8854.237345 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70450 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70450 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12105.134070 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12105.134070 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12105.340874 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12105.340874 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 73492 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 466.319606 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 236677467 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 74004 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3198.171275 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 115561804500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 466.319606 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.910780 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.910780 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 236677467 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 236677467 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 236677467 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 236677467 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 81779 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 81779 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 81779 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 81779 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 81779 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 81779 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1323960223 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1323960223 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1323960223 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000345 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000345 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000345 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000345 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000345 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16189.489025 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 16189.489025 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 16189.489025 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 16189.489025 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 73492 # number of writebacks
|
|
system.cpu.icache.writebacks::total 73492 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7746 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 7746 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 7746 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74033 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 74033 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 74033 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 74033 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 74033 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 74033 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1098365314 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1098365314 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1098365314 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1098365314 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1098365314 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1098365314 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14836.158389 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14836.158389 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 8513149 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 8514588 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 439 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 743612 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 395043 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 15130.846704 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3180527 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 410976 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 7.738960 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 170568441000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 13790.709252 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000317 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1340.137135 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.841718 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081795 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.923514 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1071 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 14862 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 25 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 244 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 802 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4899 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3369 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.065369 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907104 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 94912633 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 94912633 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 2358534 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 2358534 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 511979 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 511979 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 516918 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 516918 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65874 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 65874 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140936 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 2140936 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 65874 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2657854 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2723728 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 65874 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2657854 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2723728 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 5055 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 5055 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8128 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 8128 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158323 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 158323 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 8128 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 163378 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 171506 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 8128 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 163378 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 171506 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 60000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 483012500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 483012500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 589814000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 589814000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12070914500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12070914500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 589814000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 12553927000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 13143741000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 589814000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 12553927000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 13143741000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2358534 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 2358534 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 511979 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 511979 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 521973 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 521973 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74002 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 74002 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299259 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 2299259 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 74002 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2821232 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2895234 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 74002 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2821232 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2895234 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.964286 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009684 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.009684 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109835 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109835 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.068858 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.068858 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109835 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.057910 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.059237 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109835 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.057910 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.059237 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2222.222222 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2222.222222 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95551.434224 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95551.434224 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72565.698819 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72565.698819 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76242.330552 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76242.330552 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 76637.208028 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 76637.208028 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 292085 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 292085 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1398 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1398 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4146 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4146 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5544 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5551 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154177 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8121 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 157834 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 165955 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8121 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 157834 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 351023 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 516978 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18646833753 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 389000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 949589 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 419375 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 98517 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 31 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 3653 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 3653 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 813662 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 813662 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|