186 lines
20 KiB
Text
186 lines
20 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.212344 # Number of seconds simulated
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sim_ticks 212344043000 # Number of ticks simulated
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final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1152169 # Simulator instruction rate (inst/s)
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host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 896053064 # Simulator tick rate (ticks/s)
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host_mem_usage 309060 # Number of bytes of host memory used
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host_seconds 236.98 # Real time elapsed on the host
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sim_insts 273037663 # Number of instructions simulated
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sim_ops 349065399 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory
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system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 10715621794 # Throughput (bytes/s)
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system.membus.data_through_bus 2275398455 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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system.cpu.numCycles 424688087 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 273037663 # Number of instructions committed
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system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
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system.cpu.num_func_calls 12448615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls
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system.cpu.num_int_insts 279584918 # number of integer instructions
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system.cpu.num_fp_insts 114216705 # number of float instructions
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system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read
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system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
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system.cpu.num_mem_refs 177024356 # number of memory refs
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system.cpu.num_load_insts 94648757 # Number of load instructions
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system.cpu.num_store_insts 82375599 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 424688087 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 30563502 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction
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system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
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system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
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system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 349065594 # Class of executed instruction
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---------- End Simulation Statistics ----------
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