Ali Saidi ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts ... getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28		2006-12-06 14:29:10 -05:00
..
Benchmarks.py	Add mutex test to Benchmarks.py.	2006-10-22 12:52:58 -04:00
Caches.py	Add L2 cache option to fs.py --l2cache	2006-11-15 18:22:15 -05:00
cpu2000.py	Implement a single config file to encompass all of the SPEC	2006-11-16 13:10:38 -08:00
FSConfig.py	Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts	2006-12-06 14:29:10 -05:00
Options.py	decouple the switch option from the warmup period option - parsing was confused otherwise, oops.	2006-10-30 14:12:15 -05:00
Simulation.py	Include check for making sure caches are enabled.	2006-11-26 11:46:58 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00