gem5/configs/common
2012-03-16 07:46:45 -05:00
..
Benchmarks.py configs: fix minor config bugs posted on the mailing list 2012-02-12 17:18:53 -06:00
CacheConfig.py x86: Fix switching of CPUs 2012-03-01 11:37:02 -06:00
Caches.py O3: Remove hardcoded tgts_per_mshr in O3CPU.py. 2011-12-01 00:15:22 -08:00
cpu2000.py cpu2000: Add missing art benchmark to all 2012-01-09 18:08:20 -06:00
FSConfig.py FSConfig.py: fix a typo makeLinuxAlphaRubySystem 2012-03-16 07:46:45 -05:00
O3_ARM_v7a.py prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
Options.py CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
Simulation.py CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
SysPaths.py make rcS files read from the m5 source directory, not /dist. 2006-11-08 14:10:25 -05:00