Bootloader I had on my sytem was an older version with a couple of instruction differences.
2230 lines
256 KiB
Text
2230 lines
256 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.817969 # Number of seconds simulated
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sim_ticks 2817968959500 # Number of ticks simulated
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final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 311387 # Simulator instruction rate (inst/s)
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host_op_rate 378101 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6951332904 # Simulator tick rate (ticks/s)
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host_mem_usage 560824 # Number of bytes of host memory used
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host_seconds 405.39 # Real time elapsed on the host
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sim_insts 126231916 # Number of instructions simulated
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sim_ops 153276567 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory
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system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory
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system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 92768 # Number of read requests accepted
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system.physmem.writeReqs 67796 # Number of write requests accepted
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system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 6044 # Per bank write bursts
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system.physmem.perBankRdBursts::1 5813 # Per bank write bursts
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system.physmem.perBankRdBursts::2 5577 # Per bank write bursts
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system.physmem.perBankRdBursts::3 6085 # Per bank write bursts
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system.physmem.perBankRdBursts::4 5556 # Per bank write bursts
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system.physmem.perBankRdBursts::5 5466 # Per bank write bursts
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system.physmem.perBankRdBursts::6 6173 # Per bank write bursts
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system.physmem.perBankRdBursts::7 6793 # Per bank write bursts
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system.physmem.perBankRdBursts::8 6458 # Per bank write bursts
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system.physmem.perBankRdBursts::9 6393 # Per bank write bursts
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system.physmem.perBankRdBursts::10 5737 # Per bank write bursts
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system.physmem.perBankRdBursts::11 5119 # Per bank write bursts
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system.physmem.perBankRdBursts::12 5308 # Per bank write bursts
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system.physmem.perBankRdBursts::13 5463 # Per bank write bursts
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system.physmem.perBankRdBursts::14 5329 # Per bank write bursts
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system.physmem.perBankRdBursts::15 5386 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4258 # Per bank write bursts
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system.physmem.perBankWrBursts::1 3939 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4228 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4685 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4137 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4140 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4393 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4905 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4554 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4640 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4209 # Per bank write bursts
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system.physmem.perBankWrBursts::11 3550 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4025 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4273 # Per bank write bursts
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system.physmem.perBankWrBursts::14 3934 # Per bank write bursts
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system.physmem.perBankWrBursts::15 3898 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
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system.physmem.totGap 2816402817000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 1 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 92767 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 2 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 67794 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1185318250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 2923443250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12786.60 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31536.60 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 76736 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 50876 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 17540686.69 # Average gap between requests
|
|
system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2704844337250 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 94098160000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 19026368250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 70810447635 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 69981022395 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1628666801250 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1629394367250 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1884329288175 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1884181443990 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 668.683537 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 668.631072 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.trans_dist::ReadReq 74236 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 92896 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 137042 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 137042 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 579191 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 652018 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 17102699 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19429163 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 125 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 304844 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 304844 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.l2c.tags.replacements 100821 # number of replacements
|
|
system.l2c.tags.tagsinuse 65118.790980 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 49797.187018 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2854.503750 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966166 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 3505.210474 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 1537.513263 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3115 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 8083 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53656 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 27447983 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 27447983 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4963 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 2545 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 856871 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 242835 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 1453 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 744 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 248099 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 77823 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 27437 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 6484 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 674506 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 203103 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2346863 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 692569 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 692569 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 40 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 54 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 81755 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 19470 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 56351 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 157576 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4963 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 2545 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 856871 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 324590 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 1453 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 744 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 248099 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 97293 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 27437 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 6484 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 674506 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 259454 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2504439 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4963 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 2545 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 856871 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 324590 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 1453 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 744 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 248099 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 97293 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 27437 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 6484 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 674506 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 259454 # number of overall hits
|
|
system.l2c.overall_hits::total 2504439 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
|
|
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|
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|
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|
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|
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|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 1066 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 1432 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14112 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 62374 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 76486 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2046 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 16687 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 95 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 8066 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 66905 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 93800 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2046 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 16687 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 95 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 8066 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 66905 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 93800 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122695750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 160078750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 514237000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 307639996 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1110877246 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3660366 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10666566 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 14326932 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813881009 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3892439774 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 4706320783 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 122695750 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 973959759 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 514237000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 4200079770 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 5817198029 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 122695750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 973959759 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 514237000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 4200079770 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 5817198029 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943995500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1580248500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 2524244000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 723617500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1233115000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1667613000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2813363500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4480976500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032028 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021817 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.007272 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989189 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.963834 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.516781 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420225 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525365 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.258007 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.973994 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.793832 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.toL2Bus.trans_dist::ReadReq 2443720 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2443717 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616607 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 6218457 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 213301511 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 51755 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 14476225 # DTB read hits
|
|
system.cpu0.dtb.read_misses 4878 # DTB read misses
|
|
system.cpu0.dtb.write_hits 11074159 # DTB write hits
|
|
system.cpu0.dtb.write_misses 931 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 14481103 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 11075090 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 25550384 # DTB hits
|
|
system.cpu0.dtb.misses 5809 # DTB misses
|
|
system.cpu0.dtb.accesses 25556193 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 67954632 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2810 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 67957442 # ITB inst accesses
|
|
system.cpu0.itb.hits 67954632 # DTB hits
|
|
system.cpu0.itb.misses 2810 # DTB misses
|
|
system.cpu0.itb.accesses 67957442 # DTB accesses
|
|
system.cpu0.numCycles 82556870 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 66160123 # Number of instructions committed
|
|
system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 7292026 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 70891568 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5582 # number of float instructions
|
|
system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 29383072 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 26220754 # number of memory refs
|
|
system.cpu0.num_load_insts 14652166 # Number of load instructions
|
|
system.cpu0.num_store_insts 11568588 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 77950731.061702 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 4606138.938298 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.055794 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.944206 # Percentage of idle cycles
|
|
system.cpu0.Branches 16465385 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 55784741 67.97% 67.97% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 58719 0.07% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 14652166 17.85% 85.90% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 11568588 14.10% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 82070947 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3056 # number of quiesce instructions executed
|
|
system.cpu0.icache.tags.replacements 1798781 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.545341 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 100889008 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1799292 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 56.071504 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.678395 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.508688 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.358258 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932966 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042009 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024137 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 67090158 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 21677954 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 67090158 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 21677954 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 67090158 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 21677954 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 100889008 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 250147 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 732935 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1849597 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 866515 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 250147 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 732935 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1849597 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 866515 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 250147 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 732935 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1849597 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3389079250 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10061046680 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 13450125930 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 3389079250 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 10061046680 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 13450125930 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956673 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928101 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 67956673 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 21928101 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 67956673 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 21928101 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011408 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057021 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.018003 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012751 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011408 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057021 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.018003 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012751 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011408 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057021 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.018003 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.350570 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 7271.922440 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 7271.922440 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 5408 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.859238 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50271 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 50271 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 50271 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 50271 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 50271 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 50271 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250147 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682664 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 932811 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 250147 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 682664 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 932811 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 250147 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 682664 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 932811 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888042750 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8209155812 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11097198562 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888042750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8209155812 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11097198562 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888042750 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8209155812 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11097198562 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009079 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009079 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009079 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.513401 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 833731 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032483 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018578 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 198572858 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 198572858 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 13788624 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 4405133 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 8515109 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 26708866 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 10680775 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3155078 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 5164116 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18999969 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190600 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60611 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130493 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 381704 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235254 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80501 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135396 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 451151 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236603 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83020 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140074 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 459697 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 24469399 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 7560211 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 13679225 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 45708835 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 24659999 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 7620822 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 13809718 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 46090539 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 190274 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 59406 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 316505 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 566185 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 145437 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 33952 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 1529558 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1708947 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 55030 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20141 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65518 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 140689 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4445 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3284 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9694 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 17423 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 13 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 335711 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 93358 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 1846063 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2275132 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 390741 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 113499 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 1911581 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2415821 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905009250 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5267719081 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 6172728331 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312527367 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70730774620 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 72043301987 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46439000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 2217536617 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 75998493701 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 78216030318 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 2217536617 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 75998493701 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 78216030318 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978898 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464539 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8831614 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 27275051 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 10826212 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 3189030 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 6693674 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 20708916 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 245630 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 80752 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196011 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 522393 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239699 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83785 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145090 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 468574 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236605 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 83020 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140087 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 459712 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 24805110 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 7653569 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 15525288 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 47983967 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 25050740 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 7734321 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 15721299 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 48506360 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013612 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013306 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035838 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.020758 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013434 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010646 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228508 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.082522 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224036 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249418 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334257 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269316 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018544 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039196 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066814 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037183 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000033 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013534 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012198 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118907 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.047414 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015598 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014675 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121592 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.049804 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15234.307141 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16643.399254 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.322544 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.545514 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.043306 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41167.876557 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 34378.677948 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.939691 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39756.878574 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 32376.583496 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 377833 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 25059 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 25141 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 516 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.028559 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 48.563953 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 692569 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 692569 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 109 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155609 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 155718 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1409743 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1409743 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1933 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6811 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8744 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 109 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 1565352 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1565461 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 109 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 1565352 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1565461 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59297 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160896 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 220193 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33952 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 119815 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 153767 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19750 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43915 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 63665 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1351 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2883 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4234 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 13 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 93249 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 280711 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 373960 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 112999 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 324626 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 437625 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238574617 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677176319 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022354867 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 9593711781 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275610367 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10505789787 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777844500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1314970500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092815000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1797210500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3008091000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012184 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018081 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.007793 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014610 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020649 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.166618 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.987715 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.684233 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.379562 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.323056 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.374835 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 4634872 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1584 # DTB read misses
|
|
system.cpu1.dtb.write_hits 3276619 # DTB write hits
|
|
system.cpu1.dtb.write_misses 228 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 4636456 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 3276847 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 7911491 # DTB hits
|
|
system.cpu1.dtb.misses 1812 # DTB misses
|
|
system.cpu1.dtb.accesses 7913303 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 21928101 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 848 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 21928949 # ITB inst accesses
|
|
system.cpu1.itb.hits 21928101 # DTB hits
|
|
system.cpu1.itb.misses 848 # DTB misses
|
|
system.cpu1.itb.accesses 21928949 # DTB accesses
|
|
system.cpu1.numCycles 158012618 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 21219739 # Number of instructions committed
|
|
system.cpu1.committedOps 25418009 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 22602370 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 2405283 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 22602370 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1626 # number of float instructions
|
|
system.cpu1.num_int_register_reads 41665136 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 15857680 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 92378683 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 8126078 # number of memory refs
|
|
system.cpu1.num_load_insts 4682102 # Number of load instructions
|
|
system.cpu1.num_store_insts 3443976 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles
|
|
system.cpu1.Branches 5257577 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 17988055 68.83% 68.83% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 26134331 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 17411527 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions.
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 9691496 # DTB read hits
|
|
system.cpu2.dtb.read_misses 37543 # DTB read misses
|
|
system.cpu2.dtb.write_hits 7160478 # DTB write hits
|
|
system.cpu2.dtb.write_misses 5658 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 9729039 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 7166136 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 16851974 # DTB hits
|
|
system.cpu2.dtb.misses 43201 # DTB misses
|
|
system.cpu2.dtb.accesses 16895175 # DTB accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.itb.inst_hits 12855360 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 6344 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses
|
|
system.cpu2.itb.hits 12855360 # DTB hits
|
|
system.cpu2.itb.misses 6344 # DTB misses
|
|
system.cpu2.itb.accesses 12861704 # DTB accesses
|
|
system.cpu2.numCycles 69831868 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full
|
|
system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued
|
|
system.cpu2.iq.rate 0.744849 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 107408 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 9489180 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 7465028 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.738611 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 26486298 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 38915831 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 15804910 # Number of memory references committed
|
|
system.cpu2.commit.loads 8667813 # Number of loads committed
|
|
system.cpu2.commit.membars 226604 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 8912074 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 1635579 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 113043839 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 112575250 # The number of ROB writes
|
|
system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 38852054 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes
|
|
system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads
|
|
system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes
|
|
system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328356 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328356 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 36224 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|