gem5/src/mem
Ali Saidi 027dfa01e6 stop m5 from leaking like a sieve
don't create a new physPort/virtPort every time activateContext() is called
add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs()
on the port owner as well as delete it's peer
still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic

src/cpu/thread_state.cc:
    if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it
src/mem/bus.cc:
src/mem/bus.hh:
    add ability to delete a port by usig a hash_map instead of an array to store port ids
    add a function to do deleting
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/mem_object.cc:
src/mem/mem_object.hh:
    adda function to delete port references from a memory object
src/mem/port.cc:
src/mem/port.hh:
    add a removeConn function that tell the owener to delete any references to the port and then deletes its peer

--HG--
extra : convert_revision : 272f0c8f80e1cf1ab1750d8be5a6c9aa110b06a4
2007-03-08 18:57:15 -05:00
..
cache stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
config Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
bridge.cc Update bus bridges now that snoop ranges are passed properly 2006-11-14 01:12:52 -05:00
bridge.hh Use PacketPtr everywhere 2006-10-20 00:10:12 -07:00
bus.cc stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
bus.hh stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
dram.cc make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
dram.hh Use PacketPtr everywhere 2006-10-20 00:10:12 -07:00
mem_object.cc stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
mem_object.hh stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
packet.cc rename store conditional stuff as extra data so it can be used for conditional swaps as well 2007-02-12 13:06:30 -05:00
packet.hh Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
packet_access.hh Make byteswap work correctly on Twin??_t types. 2007-03-07 17:46:04 +00:00
page_table.cc Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. 2007-03-07 20:04:46 +00:00
page_table.hh add code to serialize se structures. Lisa is working on the python side of things and will test 2006-10-17 19:38:36 -04:00
physical.cc some forgotten commits 2007-02-12 18:40:08 -05:00
physical.hh rename store conditional stuff as extra data so it can be used for conditional swaps as well 2007-02-12 13:06:30 -05:00
port.cc stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
port.hh stop m5 from leaking like a sieve 2007-03-08 18:57:15 -05:00
port_impl.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
request.hh Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
tport.cc Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
tport.hh Merge ktlim@zizzer:/bk/newmem 2006-10-31 14:37:19 -05:00
translating_port.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
translating_port.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
vport.cc implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00
vport.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00