01f792a367
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
163 lines
5.2 KiB
Python
163 lines
5.2 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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addToPath('../ruby')
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addToPath('../topologies')
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import Options
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import Ruby
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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parser.add_option("--maxloads", metavar="N", default=100,
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help="Stop after N loads")
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parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
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help="Wakeup every N cycles")
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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#
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# Create the ruby random tester
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#
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# Check the protocol
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check_flush = False
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if buildEnv['PROTOCOL'] == 'MOESI_hammer':
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check_flush = True
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tester = RubyTester(check_flush = check_flush,
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checks_to_complete = options.maxloads,
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wakeup_frequency = options.wakeup_freq)
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#
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# Create the M5 system. Note that the Memory Object isn't
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# actually used by the rubytester, but is included to support the
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# M5 memory size == Ruby memory size checks
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#
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system = System(cpu = tester, physmem = SimpleMemory(),
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mem_ranges = [AddrRange(options.mem_size)])
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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Ruby.create_system(options, system)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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assert(options.num_cpus == len(system.ruby._cpu_ports))
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tester.num_cpus = len(system.ruby._cpu_ports)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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for ruby_port in system.ruby._cpu_ports:
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#
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# Tie the ruby tester ports to the ruby cpu read and write ports
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#
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if ruby_port.support_data_reqs:
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tester.cpuDataPort = ruby_port.slave
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if ruby_port.support_inst_reqs:
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tester.cpuInstPort = ruby_port.slave
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#
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# Tell each sequencer this is the ruby tester so that it
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# copies the subblock back to the checker
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#
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ruby_port.using_ruby_tester = True
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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ruby_port.access_phys_mem = False
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.abs_max_tick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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