592f35ac0f
src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
203 lines
7.2 KiB
C++
203 lines
7.2 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/sparc/floatregfile.hh"
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#include "base/trace.hh"
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#include "sim/byteswap.hh"
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#include "sim/serialize.hh"
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#include <string.h>
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using namespace SparcISA;
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using namespace std;
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class Checkpoint;
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string SparcISA::getFloatRegName(RegIndex index)
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{
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static std::string floatRegName[NumFloatRegs] =
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{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
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"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
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"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
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"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63"};
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return floatRegName[index];
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}
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void FloatRegFile::clear()
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{
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memset(regSpace, 0, sizeof(regSpace));
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}
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FloatReg FloatRegFile::readReg(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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FloatReg result;
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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float32_t fresult32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result32 = htog(result32);
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memcpy(&fresult32, &result32, sizeof(result32));
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result = fresult32;
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DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32);
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break;
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case DoubleWidth:
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uint64_t result64;
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float64_t fresult64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result64 = htog(result64);
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memcpy(&fresult64, &result64, sizeof(result64));
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result = fresult64;
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DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64);
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break;
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case QuadWidth:
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return result;
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}
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FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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FloatRegBits result;
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result = htog(result32);
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DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result);
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break;
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case DoubleWidth:
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uint64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result = htog(result64);
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DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
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break;
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case QuadWidth:
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return result;
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}
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Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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uint32_t result32;
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uint64_t result64;
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float32_t fresult32;
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float64_t fresult64;
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switch(width)
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{
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case SingleWidth:
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fresult32 = val;
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memcpy(&result32, &fresult32, sizeof(result32));
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result32 = gtoh(result32);
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memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
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break;
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case DoubleWidth:
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fresult64 = val;
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memcpy(&result64, &fresult64, sizeof(result64));
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result64 = gtoh(result64);
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memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
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break;
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case QuadWidth:
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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uint32_t result32;
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uint64_t result64;
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switch(width)
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{
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case SingleWidth:
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result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
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DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
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break;
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case DoubleWidth:
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result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
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DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
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break;
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case QuadWidth:
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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void FloatRegFile::serialize(std::ostream &os)
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{
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uint8_t *float_reg = (uint8_t*)regSpace;
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SERIALIZE_ARRAY(float_reg,
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SingleWidth / 8 * NumFloatRegs);
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}
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void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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uint8_t *float_reg = (uint8_t*)regSpace;
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UNSERIALIZE_ARRAY(float_reg,
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SingleWidth / 8 * NumFloatRegs);
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}
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