Gabe Black 35fa5074aa X86: Ensure that the CPUID instruction always writes its outputs. ... The CPUID instruction was implemented so that it would only write its results if the instruction was successful. This works fine on the simple CPU where unwritten registers retain their old values, but on a CPU like O3 with renaming this is broken. The instruction needs to write the old values back into the registers explicitly if they aren't being changed.		2012-06-04 10:43:09 -07:00
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decoder	X86: Ensure that the CPUID instruction always writes its outputs.	2012-06-04 10:43:09 -07:00
formats	X86: Ensure that the CPUID instruction always writes its outputs.	2012-06-04 10:43:09 -07:00
insts	x86 ISA: Implement the sse3 haddps instruction.	2012-05-19 04:32:25 -07:00
microops	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
bitfields.isa	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
includes.isa	ISA: Make the decode function part of the ISA's decoder.	2012-05-25 00:55:24 -07:00
macroop.isa	gcc: Clean-up of non-C++0x compliant code, first steps	2012-03-19 06:36:09 -04:00
main.isa	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
microasm.isa	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
operands.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
outputblock.isa	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
rom.isa	X86: Implement local labels for the ROM that actually refer into the ROM.	2008-10-12 20:44:11 -07:00
specialize.isa	X86: When decoding a memory only inst, fault on reg encodings, don't assert.	2011-04-23 15:02:29 -07:00