323 lines
11 KiB
Plaintext
323 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Blake Hechtman
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*/
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machine(MachineType:SQC, "GPU SQC (L1 I Cache)")
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: Sequencer* sequencer;
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CacheMemory * L1cache;
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int TCC_select_num_bits;
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Cycles issue_latency := 80; // time to send data down to TCC
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Cycles l2_hit_latency := 18; // for 1MB L2, 20 for 2MB
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MessageBuffer * requestFromSQC, network="To", virtual_network="1", vnet_type="request";
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MessageBuffer * probeToSQC, network="From", virtual_network="1", vnet_type="request";
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MessageBuffer * responseToSQC, network="From", virtual_network="3", vnet_type="response";
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MessageBuffer * mandatoryQueue;
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{
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state_declaration(State, desc="SQC Cache States", default="SQC_State_I") {
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I, AccessPermission:Invalid, desc="Invalid";
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V, AccessPermission:Read_Only, desc="Valid";
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}
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enumeration(Event, desc="SQC Events") {
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// Core initiated
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Fetch, desc="Fetch";
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// Mem sys initiated
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Repl, desc="Replacing block from cache";
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Data, desc="Received Data";
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}
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enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
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DataArrayRead, desc="Read the data array";
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DataArrayWrite, desc="Write the data array";
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TagArrayRead, desc="Read the data array";
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TagArrayWrite, desc="Write the data array";
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}
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (diff than memory)?";
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DataBlock DataBlk, desc="data for the block";
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bool FromL2, default="false", desc="block just moved from L2";
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}
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";
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bool Shared, desc="Victim hit by shared probe";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
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int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Addr a);
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Cycles curCycle();
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// Internal functions
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Tick clockEdge();
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Entry getCacheEntry(Addr address), return_by_pointer="yes" {
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Entry cache_entry := static_cast(Entry, "pointer", L1cache.lookup(address));
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return cache_entry;
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}
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DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return tbe.DataBlk;
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} else {
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return getCacheEntry(addr).DataBlk;
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}
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes +
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functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return SQC_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return SQC_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(SQC_State_to_permission(state));
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}
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}
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void recordRequestType(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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L1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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L1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
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}
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}
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bool checkResourceAvailable(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else {
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error("Invalid RequestType type in checkResourceAvailable");
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return true;
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}
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}
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// Out Ports
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out_port(requestNetwork_out, CPURequestMsg, requestFromSQC);
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// In Ports
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in_port(responseToSQC_in, ResponseMsg, responseToSQC) {
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if (responseToSQC_in.isReady(clockEdge())) {
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peek(responseToSQC_in, ResponseMsg, block_on="addr") {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == CoherenceResponseType:TDSysResp) {
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if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
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trigger(Event:Data, in_msg.addr, cache_entry, tbe);
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} else {
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Addr victim := L1cache.cacheProbe(in_msg.addr);
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trigger(Event:Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} else {
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error("Unexpected Response Message to Core");
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}
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}
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}
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}
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in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady(clockEdge())) {
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peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
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Entry cache_entry := getCacheEntry(in_msg.LineAddress);
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TBE tbe := TBEs.lookup(in_msg.LineAddress);
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assert(in_msg.Type == RubyRequestType:IFETCH);
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trigger(Event:Fetch, in_msg.LineAddress, cache_entry, tbe);
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}
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}
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}
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// Actions
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action(ic_invCache, "ic", desc="invalidate cache") {
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if(is_valid(cache_entry)) {
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L1cache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceRequestType:RdBlk;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.InitialRequestTime := curCycle();
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}
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}
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action(a_allocate, "a", desc="allocate block") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L1cache.allocate(address, new Entry));
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}
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}
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action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
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mandatoryQueue_in.dequeue(clockEdge());
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}
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action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
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responseToSQC_in.dequeue(clockEdge());
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}
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action(l_loadDone, "l", desc="local load done") {
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assert(is_valid(cache_entry));
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sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache);
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APPEND_TRANSITION_COMMENT(cache_entry.DataBlk);
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}
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action(w_writeCache, "w", desc="write data to cache") {
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peek(responseToSQC_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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cache_entry.DataBlk := in_msg.DataBlk;
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cache_entry.Dirty := false;
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}
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}
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// Transitions
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// transitions from base
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transition({I, V}, Repl, I) {TagArrayRead, TagArrayWrite} {
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ic_invCache
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}
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transition(I, Data, V) {TagArrayRead, TagArrayWrite, DataArrayRead} {
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a_allocate;
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w_writeCache
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l_loadDone;
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pr_popResponseQueue;
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}
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transition(I, Fetch) {TagArrayRead, TagArrayWrite} {
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nS_issueRdBlkS;
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p_popMandatoryQueue;
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}
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// simple hit transitions
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transition(V, Fetch) {TagArrayRead, DataArrayRead} {
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l_loadDone;
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p_popMandatoryQueue;
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}
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}
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