668 lines
22 KiB
Plaintext
668 lines
22 KiB
Plaintext
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lisa Hsu
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*/
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machine(MachineType:SQC, "GPU SQC (L1 I Cache)")
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: Sequencer* sequencer;
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CacheMemory * L1cache;
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int TCC_select_num_bits;
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Cycles issue_latency := 80; // time to send data down to TCC
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Cycles l2_hit_latency := 18;
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MessageBuffer * requestFromSQC, network="To", virtual_network="1", vnet_type="request";
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MessageBuffer * responseFromSQC, network="To", virtual_network="3", vnet_type="response";
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MessageBuffer * unblockFromCore, network="To", virtual_network="5", vnet_type="unblock";
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MessageBuffer * probeToSQC, network="From", virtual_network="1", vnet_type="request";
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MessageBuffer * responseToSQC, network="From", virtual_network="3", vnet_type="response";
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MessageBuffer * mandatoryQueue;
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{
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state_declaration(State, desc="SQC Cache States", default="SQC_State_I") {
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I, AccessPermission:Invalid, desc="Invalid";
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S, AccessPermission:Read_Only, desc="Shared";
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I_S, AccessPermission:Busy, desc="Invalid, issued RdBlkS, have not seen response yet";
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S_I, AccessPermission:Read_Only, desc="L1 replacement, waiting for clean WB ack";
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I_C, AccessPermission:Invalid, desc="Invalid, waiting for WBAck from TCCdir for canceled WB";
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}
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enumeration(Event, desc="SQC Events") {
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// Core initiated
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Fetch, desc="Fetch";
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//TCC initiated
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TCC_AckS, desc="TCC Ack to Core Request";
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TCC_AckWB, desc="TCC Ack for WB";
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TCC_NackWB, desc="TCC Nack for WB";
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// Mem sys initiated
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Repl, desc="Replacing block from cache";
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// Probe Events
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PrbInvData, desc="probe, return M data";
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PrbInv, desc="probe, no need for data";
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PrbShrData, desc="probe downgrade, return data";
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}
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enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
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DataArrayRead, desc="Read the data array";
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DataArrayWrite, desc="Write the data array";
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TagArrayRead, desc="Read the data array";
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TagArrayWrite, desc="Write the data array";
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}
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (diff than memory)?";
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DataBlock DataBlk, desc="data for the block";
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bool FromL2, default="false", desc="block just moved from L2";
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}
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";
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bool Shared, desc="Victim hit by shared probe";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
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int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
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Tick clockEdge();
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Tick cyclesToTicks(Cycles c);
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Addr a);
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Cycles curCycle();
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// Internal functions
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Entry getCacheEntry(Addr address), return_by_pointer="yes" {
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Entry cache_entry := static_cast(Entry, "pointer", L1cache.lookup(address));
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return cache_entry;
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}
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DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return tbe.DataBlk;
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} else {
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return getCacheEntry(addr).DataBlk;
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}
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return SQC_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return SQC_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(SQC_State_to_permission(state));
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}
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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void recordRequestType(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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L1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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L1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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L1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
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}
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}
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bool checkResourceAvailable(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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return L1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else {
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error("Invalid RequestType type in checkResourceAvailable");
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return true;
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}
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}
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// Out Ports
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out_port(requestNetwork_out, CPURequestMsg, requestFromSQC);
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out_port(responseNetwork_out, ResponseMsg, responseFromSQC);
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out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
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// In Ports
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in_port(probeNetwork_in, TDProbeRequestMsg, probeToSQC) {
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if (probeNetwork_in.isReady(clockEdge())) {
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peek(probeNetwork_in, TDProbeRequestMsg, block_on="addr") {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == ProbeRequestType:PrbInv) {
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if (in_msg.ReturnData) {
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trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
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}
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} else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
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assert(in_msg.ReturnData);
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trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
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}
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}
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}
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}
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in_port(responseToSQC_in, ResponseMsg, responseToSQC) {
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if (responseToSQC_in.isReady(clockEdge())) {
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peek(responseToSQC_in, ResponseMsg, block_on="addr") {
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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if (in_msg.Type == CoherenceResponseType:TDSysResp) {
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if (in_msg.State == CoherenceState:Shared) {
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trigger(Event:TCC_AckS, in_msg.addr, cache_entry, tbe);
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} else {
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error("SQC should not receive TDSysResp other than CoherenceState:Shared");
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}
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} else if (in_msg.Type == CoherenceResponseType:TDSysWBAck) {
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trigger(Event:TCC_AckWB, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:TDSysWBNack) {
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trigger(Event:TCC_NackWB, in_msg.addr, cache_entry, tbe);
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} else {
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error("Unexpected Response Message to Core");
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}
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}
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}
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}
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in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady(clockEdge())) {
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peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
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Entry cache_entry := getCacheEntry(in_msg.LineAddress);
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TBE tbe := TBEs.lookup(in_msg.LineAddress);
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assert(in_msg.Type == RubyRequestType:IFETCH);
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if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.LineAddress)) {
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trigger(Event:Fetch, in_msg.LineAddress, cache_entry, tbe);
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} else {
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Addr victim := L1cache.cacheProbe(in_msg.LineAddress);
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trigger(Event:Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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}
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}
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}
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// Actions
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action(ic_invCache, "ic", desc="invalidate cache") {
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if(is_valid(cache_entry)) {
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L1cache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceRequestType:RdBlkS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.InitialRequestTime := curCycle();
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}
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}
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action(vc_victim, "vc", desc="Victimize E/S Data") {
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enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.Type := CoherenceRequestType:VicClean;
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out_msg.InitialRequestTime := curCycle();
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if (cache_entry.CacheState == State:S) {
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out_msg.Shared := true;
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} else {
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out_msg.Shared := false;
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}
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out_msg.InitialRequestTime := curCycle();
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}
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}
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action(a_allocate, "a", desc="allocate block") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L1cache.allocate(address, new Entry));
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}
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}
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action(t_allocateTBE, "t", desc="allocate TBE Entry") {
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check_allocate(TBEs);
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assert(is_valid(cache_entry));
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TBEs.allocate(address);
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set_tbe(TBEs.lookup(address));
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tbe.DataBlk := cache_entry.DataBlk; // Data only used for WBs
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tbe.Dirty := cache_entry.Dirty;
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tbe.Shared := false;
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}
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action(d_deallocateTBE, "d", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
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mandatoryQueue_in.dequeue(clockEdge());
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}
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action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
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responseToSQC_in.dequeue(clockEdge());
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}
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action(pp_popProbeQueue, "pp", desc="pop probe queue") {
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probeNetwork_in.dequeue(clockEdge());
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}
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action(l_loadDone, "l", desc="local load done") {
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assert(is_valid(cache_entry));
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sequencer.readCallback(address, cache_entry.DataBlk,
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false, MachineType:L1Cache);
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APPEND_TRANSITION_COMMENT(cache_entry.DataBlk);
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}
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action(xl_loadDone, "xl", desc="remote load done") {
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peek(responseToSQC_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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sequencer.readCallback(address,
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cache_entry.DataBlk,
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false,
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machineIDToMachineType(in_msg.Sender),
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in_msg.InitialRequestTime,
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in_msg.ForwardRequestTime,
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in_msg.ProbeRequestStartTime);
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APPEND_TRANSITION_COMMENT(cache_entry.DataBlk);
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}
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}
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action(w_writeCache, "w", desc="write data to cache") {
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peek(responseToSQC_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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cache_entry.DataBlk := in_msg.DataBlk;
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cache_entry.Dirty := in_msg.Dirty;
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}
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}
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action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
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peek(responseToSQC_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:StaleNotif;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Control;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(wb_data, "wb", desc="write back data") {
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peek(responseToSQC_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:CPUData;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.DataBlk := tbe.DataBlk;
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out_msg.Dirty := tbe.Dirty;
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if (tbe.Shared) {
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out_msg.NbReqShared := true;
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} else {
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out_msg.NbReqShared := false;
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}
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out_msg.State := CoherenceState:Shared; // faux info
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out_msg.MessageSize := MessageSizeType:Writeback_Data;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
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enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
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out_msg.Sender := machineID;
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// will this always be ok? probably not for multisocket
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.Dirty := false;
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out_msg.Hit := false;
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out_msg.Ntsl := true;
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out_msg.State := CoherenceState:NA;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
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enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
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out_msg.Sender := machineID;
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// will this always be ok? probably not for multisocket
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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out_msg.Dirty := false;
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out_msg.Ntsl := true;
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out_msg.Hit := false;
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out_msg.State := CoherenceState:NA;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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action(prm_sendProbeResponseMiss, "prm", desc="send probe ack PrbShrData, no data") {
|
|
enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.Dirty := false; // only true if sending back data i think
|
|
out_msg.Hit := false;
|
|
out_msg.Ntsl := false;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
|
|
action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
|
|
enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
|
|
assert(is_valid(cache_entry) || is_valid(tbe));
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp;
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.DataBlk := getDataBlock(address);
|
|
if (is_valid(tbe)) {
|
|
out_msg.Dirty := tbe.Dirty;
|
|
} else {
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
}
|
|
out_msg.Hit := true;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
|
|
enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
|
|
assert(is_valid(cache_entry) || is_valid(tbe));
|
|
assert(is_valid(cache_entry));
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp;
|
|
out_msg.Sender := machineID;
|
|
// will this always be ok? probably not for multisocket
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.DataBlk := getDataBlock(address);
|
|
if (is_valid(tbe)) {
|
|
out_msg.Dirty := tbe.Dirty;
|
|
} else {
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
}
|
|
out_msg.Hit := true;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(sf_setSharedFlip, "sf", desc="hit by shared probe, status may be different") {
|
|
assert(is_valid(tbe));
|
|
tbe.Shared := true;
|
|
}
|
|
|
|
action(uu_sendUnblock, "uu", desc="state changed, unblock") {
|
|
enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address,MachineType:TCCdir,
|
|
TCC_select_low_bit, TCC_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
|
}
|
|
}
|
|
|
|
action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
|
|
probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
|
|
}
|
|
|
|
action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
|
|
mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
|
|
}
|
|
|
|
// Transitions
|
|
|
|
// transitions from base
|
|
transition(I, Fetch, I_S) {TagArrayRead, TagArrayWrite} {
|
|
a_allocate;
|
|
nS_issueRdBlkS;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
// simple hit transitions
|
|
transition(S, Fetch) {TagArrayRead, DataArrayRead} {
|
|
l_loadDone;
|
|
p_popMandatoryQueue;
|
|
}
|
|
|
|
// recycles from transients
|
|
transition({I_S, S_I, I_C}, {Fetch, Repl}) {} {
|
|
zz_recycleMandatoryQueue;
|
|
}
|
|
|
|
transition(S, Repl, S_I) {TagArrayRead} {
|
|
t_allocateTBE;
|
|
vc_victim;
|
|
ic_invCache;
|
|
}
|
|
|
|
// TCC event
|
|
transition(I_S, TCC_AckS, S) {DataArrayRead, DataArrayWrite} {
|
|
w_writeCache;
|
|
xl_loadDone;
|
|
uu_sendUnblock;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_I, TCC_NackWB, I){TagArrayWrite} {
|
|
d_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(S_I, TCC_AckWB, I) {TagArrayWrite} {
|
|
wb_data;
|
|
d_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_C, TCC_AckWB, I){TagArrayWrite} {
|
|
ss_sendStaleNotification;
|
|
d_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(I_C, TCC_NackWB, I) {TagArrayWrite} {
|
|
d_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
// Probe transitions
|
|
transition({S, I}, PrbInvData, I) {TagArrayRead, TagArrayWrite} {
|
|
pd_sendProbeResponseData;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_C, PrbInvData, I_C) {
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({S, I}, PrbInv, I) {TagArrayRead, TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({S}, PrbShrData, S) {DataArrayRead} {
|
|
pd_sendProbeResponseData;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({I, I_C}, PrbShrData) {TagArrayRead} {
|
|
prm_sendProbeResponseMiss;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_C, PrbInv, I_C){
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_S, {PrbInv, PrbInvData}) {} {
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
a_allocate; // but make sure there is room for incoming data when it arrives
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(I_S, PrbShrData) {} {
|
|
prm_sendProbeResponseMiss;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(S_I, PrbInvData, I_C) {TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(S_I, PrbInv, I_C) {TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
ic_invCache;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(S_I, PrbShrData) {DataArrayRead} {
|
|
pd_sendProbeResponseData;
|
|
sf_setSharedFlip;
|
|
pp_popProbeQueue;
|
|
}
|
|
}
|