b63eb1302b
for HSAIL an operand's indices into the register files may be calculated trivially, because the operands are always read from a register file, or are an immediate. for machine ISA, however, an op selector may specify special registers, or may specify special SGPRs with an alias op selector value. the location of some of the special registers values are dependent on the size of the RF in some cases. here we add a way for the underlying getRegisterIndex() method to know about the size of the RFs, so that it may find the relative positions of the special register values.
251 lines
8 KiB
C++
251 lines
8 KiB
C++
/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: John Kalamatianos
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*/
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#include "gpu-compute/vector_register_file.hh"
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#include <string>
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#include "base/misc.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "gpu-compute/shader.hh"
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#include "gpu-compute/simple_pool_manager.hh"
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#include "gpu-compute/wavefront.hh"
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#include "params/VectorRegisterFile.hh"
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VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams *p)
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: SimObject(p),
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manager(new SimplePoolManager(p->min_alloc, p->num_regs_per_simd)),
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simdId(p->simd_id), numRegsPerSimd(p->num_regs_per_simd),
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vgprState(new VecRegisterState())
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{
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fatal_if(numRegsPerSimd % 2, "VRF size is illegal\n");
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fatal_if(simdId < 0, "Illegal SIMD id for VRF");
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fatal_if(numRegsPerSimd % p->min_alloc, "Min VGPR region allocation is not "
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"multiple of VRF size\n");
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busy.clear();
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busy.resize(numRegsPerSimd, 0);
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nxtBusy.clear();
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nxtBusy.resize(numRegsPerSimd, 0);
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vgprState->init(numRegsPerSimd, p->wfSize);
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}
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void
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VectorRegisterFile::setParent(ComputeUnit *_computeUnit)
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{
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computeUnit = _computeUnit;
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vgprState->setParent(computeUnit);
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}
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uint8_t
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VectorRegisterFile::regNxtBusy(int idx, uint32_t operandSize) const
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{
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uint8_t status = nxtBusy.at(idx);
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if (operandSize > 4) {
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status = status | (nxtBusy.at((idx + 1) % numRegs()));
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}
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return status;
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}
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uint8_t
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VectorRegisterFile::regBusy(int idx, uint32_t operandSize) const
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{
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uint8_t status = busy.at(idx);
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if (operandSize > 4) {
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status = status | (busy.at((idx + 1) % numRegs()));
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}
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return status;
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}
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void
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VectorRegisterFile::preMarkReg(int regIdx, uint32_t operandSize, uint8_t value)
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{
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nxtBusy.at(regIdx) = value;
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if (operandSize > 4) {
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nxtBusy.at((regIdx + 1) % numRegs()) = value;
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}
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}
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void
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VectorRegisterFile::markReg(int regIdx, uint32_t operandSize, uint8_t value)
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{
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busy.at(regIdx) = value;
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if (operandSize > 4) {
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busy.at((regIdx + 1) % numRegs()) = value;
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}
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}
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bool
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VectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const
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{
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for (int i = 0; i < ii->getNumOperands(); ++i) {
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if (ii->isVectorRegister(i)) {
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uint32_t vgprIdx = ii->getRegisterIndex(i, ii);
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uint32_t pVgpr = w->remap(vgprIdx, ii->getOperandSize(i), 1);
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if (regBusy(pVgpr, ii->getOperandSize(i)) == 1) {
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if (ii->isDstOperand(i)) {
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w->numTimesBlockedDueWAXDependencies++;
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} else if (ii->isSrcOperand(i)) {
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w->numTimesBlockedDueRAWDependencies++;
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}
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return false;
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}
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if (regNxtBusy(pVgpr, ii->getOperandSize(i)) == 1) {
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if (ii->isDstOperand(i)) {
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w->numTimesBlockedDueWAXDependencies++;
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} else if (ii->isSrcOperand(i)) {
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w->numTimesBlockedDueRAWDependencies++;
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}
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return false;
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}
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}
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}
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return true;
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}
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void
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VectorRegisterFile::exec(GPUDynInstPtr ii, Wavefront *w)
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{
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bool loadInstr = ii->isLoad();
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bool atomicInstr = ii->isAtomic() || ii->isMemFence();
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bool loadNoArgInstr = loadInstr && !ii->isArgLoad();
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// iterate over all register destination operands
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for (int i = 0; i < ii->getNumOperands(); ++i) {
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if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
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uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii),
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ii->getOperandSize(i), 1);
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// mark the destination vector register as busy
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markReg(physReg, ii->getOperandSize(i), 1);
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// clear the in-flight status of the destination vector register
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preMarkReg(physReg, ii->getOperandSize(i), 0);
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// FIXME: if we ever model correct timing behavior
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// for load argument instructions then we should not
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// set the destination register as busy now but when
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// the data returns. Loads and Atomics should free
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// their destination registers when the data returns,
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// not now
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if (!atomicInstr && !loadNoArgInstr) {
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uint32_t pipeLen = ii->getOperandSize(i) <= 4 ?
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computeUnit->spBypassLength() :
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computeUnit->dpBypassLength();
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// schedule an event for marking the register as ready
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computeUnit->registerEvent(w->simdId, physReg,
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ii->getOperandSize(i),
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computeUnit->shader->tick_cnt +
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computeUnit->shader->ticks(pipeLen),
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0);
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}
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}
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}
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}
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int
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VectorRegisterFile::exec(uint64_t dynamic_id, Wavefront *w,
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std::vector<uint32_t> ®Vec, uint32_t operandSize,
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uint64_t timestamp)
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{
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int delay = 0;
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panic_if(regVec.size() <= 0, "Illegal VGPR vector size=%d\n",
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regVec.size());
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for (int i = 0; i < regVec.size(); ++i) {
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// mark the destination VGPR as free when the timestamp expires
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computeUnit->registerEvent(w->simdId, regVec[i], operandSize,
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computeUnit->shader->tick_cnt + timestamp +
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computeUnit->shader->ticks(delay), 0);
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}
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return delay;
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}
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void
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VectorRegisterFile::updateResources(Wavefront *w, GPUDynInstPtr ii)
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{
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// iterate over all register destination operands
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for (int i = 0; i < ii->getNumOperands(); ++i) {
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if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
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uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii),
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ii->getOperandSize(i), 1);
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// set the in-flight status of the destination vector register
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preMarkReg(physReg, ii->getOperandSize(i), 1);
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}
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}
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}
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bool
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VectorRegisterFile::vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w,
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GPUDynInstPtr ii,
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VrfAccessType accessType)
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{
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bool ready = true;
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return ready;
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}
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bool
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VectorRegisterFile::vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii,
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VrfAccessType accessType)
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{
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bool ready = true;
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return ready;
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}
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VectorRegisterFile*
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VectorRegisterFileParams::create()
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{
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return new VectorRegisterFile(this);
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}
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