b63eb1302b
for HSAIL an operand's indices into the register files may be calculated trivially, because the operands are always read from a register file, or are an immediate. for machine ISA, however, an op selector may specify special registers, or may specify special SGPRs with an alias op selector value. the location of some of the special registers values are dependent on the size of the RF in some cases. here we add a way for the underlying getRegisterIndex() method to know about the size of the RFs, so that it may find the relative positions of the special register values.
541 lines
10 KiB
C++
541 lines
10 KiB
C++
/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Anthony Gutierrez
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*/
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "debug/GPUMem.hh"
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#include "gpu-compute/gpu_static_inst.hh"
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#include "gpu-compute/shader.hh"
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#include "gpu-compute/wavefront.hh"
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GPUDynInst::GPUDynInst(ComputeUnit *_cu, Wavefront *_wf,
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GPUStaticInst *static_inst, uint64_t instSeqNum)
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: GPUExecContext(_cu, _wf), addr(computeUnit()->wfSize(), (Addr)0),
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n_reg(0), useContinuation(false),
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statusBitVector(0), _staticInst(static_inst), _seqNum(instSeqNum)
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{
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tlbHitLevel.assign(computeUnit()->wfSize(), -1);
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d_data = new uint8_t[computeUnit()->wfSize() * 16];
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a_data = new uint8_t[computeUnit()->wfSize() * 8];
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x_data = new uint8_t[computeUnit()->wfSize() * 8];
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for (int i = 0; i < (computeUnit()->wfSize() * 8); ++i) {
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a_data[i] = 0;
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x_data[i] = 0;
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}
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for (int i = 0; i < (computeUnit()->wfSize() * 16); ++i) {
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d_data[i] = 0;
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}
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}
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GPUDynInst::~GPUDynInst()
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{
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delete[] d_data;
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delete[] a_data;
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delete[] x_data;
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}
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void
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GPUDynInst::execute(GPUDynInstPtr gpuDynInst)
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{
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_staticInst->execute(gpuDynInst);
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}
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int
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GPUDynInst::numSrcRegOperands()
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{
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return _staticInst->numSrcRegOperands();
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}
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int
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GPUDynInst::numDstRegOperands()
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{
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return _staticInst->numDstRegOperands();
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}
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int
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GPUDynInst::getNumOperands()
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{
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return _staticInst->getNumOperands();
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}
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bool
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GPUDynInst::isVectorRegister(int operandIdx)
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{
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return _staticInst->isVectorRegister(operandIdx);
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}
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bool
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GPUDynInst::isScalarRegister(int operandIdx)
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{
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return _staticInst->isScalarRegister(operandIdx);
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}
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bool
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GPUDynInst::isCondRegister(int operandIdx)
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{
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return _staticInst->isCondRegister(operandIdx);
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}
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int
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GPUDynInst::getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst)
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{
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return _staticInst->getRegisterIndex(operandIdx, gpuDynInst);
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}
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int
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GPUDynInst::getOperandSize(int operandIdx)
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{
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return _staticInst->getOperandSize(operandIdx);
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}
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bool
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GPUDynInst::isDstOperand(int operandIdx)
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{
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return _staticInst->isDstOperand(operandIdx);
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}
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bool
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GPUDynInst::isSrcOperand(int operandIdx)
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{
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return _staticInst->isSrcOperand(operandIdx);
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}
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const std::string&
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GPUDynInst::disassemble() const
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{
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return _staticInst->disassemble();
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}
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uint64_t
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GPUDynInst::seqNum() const
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{
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return _seqNum;
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}
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Enums::StorageClassType
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GPUDynInst::executedAs()
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{
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return _staticInst->executed_as;
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}
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// Process a memory instruction and (if necessary) submit timing request
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void
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GPUDynInst::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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DPRINTF(GPUMem, "CU%d: WF[%d][%d]: mempacket status bitvector=%#x\n",
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cu->cu_id, simdId, wfSlotId, exec_mask);
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_staticInst->initiateAcc(gpuDynInst);
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time = 0;
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}
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void
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GPUDynInst::completeAcc(GPUDynInstPtr gpuDynInst)
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{
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_staticInst->completeAcc(gpuDynInst);
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}
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/**
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* accessor methods for the attributes of
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* the underlying GPU static instruction
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*/
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bool
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GPUDynInst::isALU() const
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{
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return _staticInst->isALU();
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}
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bool
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GPUDynInst::isBranch() const
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{
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return _staticInst->isBranch();
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}
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bool
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GPUDynInst::isNop() const
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{
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return _staticInst->isNop();
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}
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bool
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GPUDynInst::isReturn() const
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{
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return _staticInst->isReturn();
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}
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bool
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GPUDynInst::isUnconditionalJump() const
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{
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return _staticInst->isUnconditionalJump();
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}
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bool
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GPUDynInst::isSpecialOp() const
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{
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return _staticInst->isSpecialOp();
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}
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bool
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GPUDynInst::isWaitcnt() const
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{
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return _staticInst->isWaitcnt();
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}
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bool
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GPUDynInst::isBarrier() const
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{
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return _staticInst->isBarrier();
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}
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bool
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GPUDynInst::isMemFence() const
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{
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return _staticInst->isMemFence();
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}
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bool
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GPUDynInst::isMemRef() const
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{
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return _staticInst->isMemRef();
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}
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bool
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GPUDynInst::isFlat() const
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{
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return _staticInst->isFlat();
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}
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bool
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GPUDynInst::isLoad() const
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{
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return _staticInst->isLoad();
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}
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bool
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GPUDynInst::isStore() const
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{
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return _staticInst->isStore();
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}
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bool
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GPUDynInst::isAtomic() const
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{
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return _staticInst->isAtomic();
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}
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bool
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GPUDynInst::isAtomicNoRet() const
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{
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return _staticInst->isAtomicNoRet();
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}
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bool
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GPUDynInst::isAtomicRet() const
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{
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return _staticInst->isAtomicRet();
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}
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bool
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GPUDynInst::isScalar() const
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{
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return _staticInst->isScalar();
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}
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bool
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GPUDynInst::readsSCC() const
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{
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return _staticInst->readsSCC();
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}
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bool
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GPUDynInst::writesSCC() const
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{
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return _staticInst->writesSCC();
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}
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bool
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GPUDynInst::readsVCC() const
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{
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return _staticInst->readsVCC();
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}
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bool
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GPUDynInst::writesVCC() const
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{
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return _staticInst->writesVCC();
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}
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bool
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GPUDynInst::isAtomicAnd() const
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{
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return _staticInst->isAtomicAnd();
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}
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bool
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GPUDynInst::isAtomicOr() const
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{
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return _staticInst->isAtomicOr();
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}
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bool
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GPUDynInst::isAtomicXor() const
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{
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return _staticInst->isAtomicXor();
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}
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bool
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GPUDynInst::isAtomicCAS() const
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{
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return _staticInst->isAtomicCAS();
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}
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bool GPUDynInst::isAtomicExch() const
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{
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return _staticInst->isAtomicExch();
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}
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bool
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GPUDynInst::isAtomicAdd() const
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{
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return _staticInst->isAtomicAdd();
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}
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bool
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GPUDynInst::isAtomicSub() const
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{
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return _staticInst->isAtomicSub();
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}
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bool
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GPUDynInst::isAtomicInc() const
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{
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return _staticInst->isAtomicInc();
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}
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bool
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GPUDynInst::isAtomicDec() const
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{
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return _staticInst->isAtomicDec();
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}
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bool
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GPUDynInst::isAtomicMax() const
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{
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return _staticInst->isAtomicMax();
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}
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bool
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GPUDynInst::isAtomicMin() const
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{
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return _staticInst->isAtomicMin();
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}
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bool
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GPUDynInst::isArgLoad() const
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{
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return _staticInst->isArgLoad();
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}
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bool
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GPUDynInst::isGlobalMem() const
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{
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return _staticInst->isGlobalMem();
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}
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bool
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GPUDynInst::isLocalMem() const
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{
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return _staticInst->isLocalMem();
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}
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bool
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GPUDynInst::isArgSeg() const
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{
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return _staticInst->isArgSeg();
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}
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bool
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GPUDynInst::isGlobalSeg() const
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{
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return _staticInst->isGlobalSeg();
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}
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bool
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GPUDynInst::isGroupSeg() const
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{
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return _staticInst->isGroupSeg();
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}
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bool
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GPUDynInst::isKernArgSeg() const
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{
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return _staticInst->isKernArgSeg();
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}
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bool
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GPUDynInst::isPrivateSeg() const
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{
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return _staticInst->isPrivateSeg();
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}
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bool
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GPUDynInst::isReadOnlySeg() const
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{
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return _staticInst->isReadOnlySeg();
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}
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bool
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GPUDynInst::isSpillSeg() const
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{
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return _staticInst->isSpillSeg();
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}
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bool
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GPUDynInst::isWorkitemScope() const
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{
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return _staticInst->isWorkitemScope();
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}
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bool
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GPUDynInst::isWavefrontScope() const
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{
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return _staticInst->isWavefrontScope();
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}
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bool
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GPUDynInst::isWorkgroupScope() const
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{
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return _staticInst->isWorkgroupScope();
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}
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bool
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GPUDynInst::isDeviceScope() const
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{
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return _staticInst->isDeviceScope();
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}
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bool
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GPUDynInst::isSystemScope() const
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{
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return _staticInst->isSystemScope();
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}
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bool
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GPUDynInst::isNoScope() const
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{
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return _staticInst->isNoScope();
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}
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bool
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GPUDynInst::isRelaxedOrder() const
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{
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return _staticInst->isRelaxedOrder();
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}
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bool
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GPUDynInst::isAcquire() const
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{
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return _staticInst->isAcquire();
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}
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bool
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GPUDynInst::isRelease() const
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{
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return _staticInst->isRelease();
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}
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bool
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GPUDynInst::isAcquireRelease() const
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{
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return _staticInst->isAcquireRelease();
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}
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bool
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GPUDynInst::isNoOrder() const
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{
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return _staticInst->isNoOrder();
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}
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bool
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GPUDynInst::isGloballyCoherent() const
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{
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return _staticInst->isGloballyCoherent();
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}
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bool
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GPUDynInst::isSystemCoherent() const
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{
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return _staticInst->isSystemCoherent();
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}
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void
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GPUDynInst::updateStats()
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{
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if (_staticInst->isLocalMem()) {
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// access to LDS (shared) memory
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cu->dynamicLMemInstrCnt++;
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} else {
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// access to global memory
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// update PageDivergence histogram
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int number_pages_touched = cu->pagesTouched.size();
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assert(number_pages_touched);
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cu->pageDivergenceDist.sample(number_pages_touched);
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std::pair<ComputeUnit::pageDataStruct::iterator, bool> ret;
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for (auto it : cu->pagesTouched) {
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// see if this page has been touched before. if not, this also
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// inserts the page into the table.
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ret = cu->pageAccesses
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.insert(ComputeUnit::pageDataStruct::value_type(it.first,
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std::make_pair(1, it.second)));
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// if yes, then update the stats
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if (!ret.second) {
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ret.first->second.first++;
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ret.first->second.second += it.second;
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}
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}
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cu->pagesTouched.clear();
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// total number of memory instructions (dynamic)
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// Atomics are counted as a single memory instruction.
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// this is # memory instructions per wavefronts, not per workitem
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cu->dynamicGMemInstrCnt++;
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}
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}
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