183 lines
5.3 KiB
C++
183 lines
5.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "cpu/o3/rename_map.hh"
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#include <vector>
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#include "debug/Rename.hh"
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using namespace std;
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/**** SimpleRenameMap methods ****/
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SimpleRenameMap::SimpleRenameMap()
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: freeList(NULL), zeroReg(0)
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{
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}
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void
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SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
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RegIndex _zeroReg)
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{
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assert(freeList == NULL);
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assert(map.empty());
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map.resize(size);
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freeList = _freeList;
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zeroReg = _zeroReg;
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}
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SimpleRenameMap::RenameInfo
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SimpleRenameMap::rename(RegIndex arch_reg)
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{
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PhysRegIndex renamed_reg;
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// Record the current physical register that is renamed to the
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// requested architected register.
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PhysRegIndex prev_reg = map[arch_reg];
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// If it's not referencing the zero register, then rename the
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// register.
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if (arch_reg != zeroReg) {
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renamed_reg = freeList->getReg();
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map[arch_reg] = renamed_reg;
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} else {
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// Otherwise return the zero register so nothing bad happens.
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assert(prev_reg == zeroReg);
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renamed_reg = zeroReg;
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}
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DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
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arch_reg, renamed_reg, prev_reg);
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return RenameInfo(renamed_reg, prev_reg);
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}
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/**** UnifiedRenameMap methods ****/
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void
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UnifiedRenameMap::init(PhysRegFile *_regFile,
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RegIndex _intZeroReg,
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RegIndex _floatZeroReg,
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UnifiedFreeList *freeList)
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{
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regFile = _regFile;
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intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
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floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
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ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
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}
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UnifiedRenameMap::RenameInfo
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UnifiedRenameMap::rename(RegIndex arch_reg)
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{
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RegIndex rel_arch_reg;
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switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
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case IntRegClass:
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return renameInt(rel_arch_reg);
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case FloatRegClass:
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return renameFloat(rel_arch_reg);
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case CCRegClass:
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return renameCC(rel_arch_reg);
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case MiscRegClass:
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return renameMisc(rel_arch_reg);
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default:
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panic("rename rename(): unknown reg class %s\n",
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RegClassStrings[regIdxToClass(arch_reg)]);
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}
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}
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PhysRegIndex
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UnifiedRenameMap::lookup(RegIndex arch_reg) const
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{
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RegIndex rel_arch_reg;
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switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
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case IntRegClass:
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return lookupInt(rel_arch_reg);
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case FloatRegClass:
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return lookupFloat(rel_arch_reg);
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case CCRegClass:
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return lookupCC(rel_arch_reg);
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case MiscRegClass:
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return lookupMisc(rel_arch_reg);
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default:
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panic("rename lookup(): unknown reg class %s\n",
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RegClassStrings[regIdxToClass(arch_reg)]);
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}
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}
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void
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UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
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{
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RegIndex rel_arch_reg;
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switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
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case IntRegClass:
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return setIntEntry(rel_arch_reg, phys_reg);
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case FloatRegClass:
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return setFloatEntry(rel_arch_reg, phys_reg);
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case CCRegClass:
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return setCCEntry(rel_arch_reg, phys_reg);
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case MiscRegClass:
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// Misc registers do not actually rename, so don't change
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// their mappings. We end up here when a commit or squash
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// tries to update or undo a hardwired misc reg nmapping,
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// which should always be setting it to what it already is.
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assert(phys_reg == lookupMisc(rel_arch_reg));
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return;
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default:
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panic("rename setEntry(): unknown reg class %s\n",
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RegClassStrings[regIdxToClass(arch_reg)]);
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}
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}
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