eb19fc2976
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows. A probe point is added in the Fetch stage for probing when a fetch request is sent. Notify is fired on the probe point when a request is sent succesfully in the first attempt as well as on a retry attempt. Probe points are added in the IEW stage when an instruction begins to execute and when execution is complete. This points can be used for monitoring the execution time of an instruction. Probe points are added in the Rename stage to probe renaming of source and destination registers and when there is squashing. These probe points can be used to track register dependencies and remove when there is squashing. A probe point for squashing is added in Commit to probe squashed instructions.
532 lines
18 KiB
C++
532 lines
18 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_RENAME_HH__
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#define __CPU_O3_RENAME_HH__
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#include <list>
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#include <utility>
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#include "base/statistics.hh"
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#include "config/the_isa.hh"
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#include "cpu/timebuf.hh"
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#include "sim/probe/probe.hh"
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struct DerivO3CPUParams;
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/**
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* DefaultRename handles both single threaded and SMT rename. Its
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* width is specified by the parameters; each cycle it tries to rename
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* that many instructions. It holds onto the rename history of all
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* instructions with destination registers, storing the
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* arch. register, the new physical register, and the old physical
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* register, to allow for undoing of mappings if squashing happens, or
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* freeing up registers upon commit. Rename handles blocking if the
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* ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
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* and does so by stalling on the instruction until the ROB is empty
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* and there are no instructions in flight to the ROB.
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*/
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template<class Impl>
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class DefaultRename
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{
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public:
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// Typedefs from the Impl.
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::O3CPU O3CPU;
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// Typedefs from the CPUPol
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typedef typename CPUPol::DecodeStruct DecodeStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::FreeList FreeList;
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typedef typename CPUPol::RenameMap RenameMap;
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// These are used only for initialization.
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typedef typename CPUPol::IEW IEW;
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typedef typename CPUPol::Commit Commit;
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// Typedefs from the ISA.
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typedef TheISA::RegIndex RegIndex;
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// A deque is used to queue the instructions. Barrier insts must
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// be added to the front of the queue, which is the only reason for
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// using a deque instead of a queue. (Most other stages use a
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// queue)
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typedef std::deque<DynInstPtr> InstQueue;
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public:
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/** Overall rename status. Used to determine if the CPU can
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* deschedule itself due to a lack of activity.
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*/
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enum RenameStatus {
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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StartSquash,
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Squashing,
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Blocked,
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Unblocking,
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SerializeStall
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};
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private:
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/** Rename status. */
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RenameStatus _status;
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/** Per-thread status. */
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ThreadStatus renameStatus[Impl::MaxThreads];
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/** Probe points. */
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typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair;
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/** To probe when register renaming for an instruction is complete */
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ProbePointArg<DynInstPtr> *ppRename;
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/**
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* To probe when an instruction is squashed and the register mapping
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* for it needs to be undone
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*/
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ProbePointArg<SeqNumRegPair> *ppSquashInRename;
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public:
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/** DefaultRename constructor. */
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DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
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/** Returns the name of rename. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Registers probes. */
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void regProbePoints();
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/** Sets the main backwards communication time buffer pointer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Sets pointer to time buffer used to communicate to the next stage. */
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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/** Sets pointer to time buffer coming from decode. */
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void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
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/** Sets pointer to IEW stage. Used only for initialization. */
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void setIEWStage(IEW *iew_stage)
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{ iew_ptr = iew_stage; }
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/** Sets pointer to commit stage. Used only for initialization. */
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void setCommitStage(Commit *commit_stage)
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{ commit_ptr = commit_stage; }
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private:
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/** Pointer to IEW stage. Used only for initialization. */
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IEW *iew_ptr;
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/** Pointer to commit stage. Used only for initialization. */
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Commit *commit_ptr;
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public:
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/** Initializes variables for the stage. */
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void startupStage();
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets pointer to rename maps (per-thread structures). */
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void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
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/** Sets pointer to the free list. */
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void setFreeList(FreeList *fl_ptr);
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/** Sets pointer to the scoreboard. */
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void setScoreboard(Scoreboard *_scoreboard);
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/** Has the stage drained? */
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bool isDrained() const;
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Squashes all instructions in a thread. */
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void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
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/** Ticks rename, which processes all input signals and attempts to rename
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* as many instructions as possible.
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*/
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void tick();
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/** Debugging function used to dump history buffer of renamings. */
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void dumpHistory();
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private:
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/** Reset this pipeline stage */
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void resetStage();
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/** Determines what to do based on rename's current status.
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* @param status_change rename() sets this variable if there was a status
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* change (ie switching from blocking to unblocking).
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* @param tid Thread id to rename instructions from.
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*/
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void rename(bool &status_change, ThreadID tid);
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/** Renames instructions for the given thread. Also handles serializing
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* instructions.
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*/
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void renameInsts(ThreadID tid);
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/** Inserts unused instructions from a given thread into the skid buffer,
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* to be renamed once rename unblocks.
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*/
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void skidInsert(ThreadID tid);
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/** Separates instructions from decode into individual lists of instructions
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* sorted by thread.
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*/
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void sortInsts();
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/** Returns if all of the skid buffers are empty. */
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bool skidsEmpty();
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/** Updates overall rename status based on all of the threads' statuses. */
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void updateStatus();
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/** Switches rename to blocking, and signals back that rename has become
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* blocked.
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* @return Returns true if there is a status change.
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*/
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bool block(ThreadID tid);
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/** Switches rename to unblocking if the skid buffer is empty, and signals
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* back that rename has unblocked.
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* @return Returns true if there is a status change.
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*/
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bool unblock(ThreadID tid);
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/** Executes actual squash, removing squashed instructions. */
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void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
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/** Removes a committed instruction's rename history. */
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void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
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/** Renames the source registers of an instruction. */
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inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
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/** Renames the destination registers of an instruction. */
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inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
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/** Calculates the number of free ROB entries for a specific thread. */
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inline int calcFreeROBEntries(ThreadID tid);
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/** Calculates the number of free IQ entries for a specific thread. */
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inline int calcFreeIQEntries(ThreadID tid);
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/** Calculates the number of free LQ entries for a specific thread. */
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inline int calcFreeLQEntries(ThreadID tid);
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/** Calculates the number of free SQ entries for a specific thread. */
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inline int calcFreeSQEntries(ThreadID tid);
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/** Returns the number of valid instructions coming from decode. */
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unsigned validInsts();
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/** Reads signals telling rename to block/unblock. */
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void readStallSignals(ThreadID tid);
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/** Checks if any stages are telling rename to block. */
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bool checkStall(ThreadID tid);
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/** Gets the number of free entries for a specific thread. */
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void readFreeEntries(ThreadID tid);
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/** Checks the signals and updates the status. */
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bool checkSignalsAndUpdate(ThreadID tid);
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/** Either serializes on the next instruction available in the InstQueue,
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* or records that it must serialize on the next instruction to enter
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* rename.
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* @param inst_list The list of younger, unprocessed instructions for the
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* thread that has the serializeAfter instruction.
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* @param tid The thread id.
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*/
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void serializeAfter(InstQueue &inst_list, ThreadID tid);
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/** Holds the information for each destination register rename. It holds
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* the instruction's sequence number, the arch register, the old physical
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* register for that arch. register, and the new physical register.
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*/
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struct RenameHistory {
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RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
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PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
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: instSeqNum(_instSeqNum), archReg(_archReg),
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newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
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{
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}
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/** The sequence number of the instruction that renamed. */
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InstSeqNum instSeqNum;
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/** The architectural register index that was renamed. */
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RegIndex archReg;
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/** The new physical register that the arch. register is renamed to. */
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PhysRegIndex newPhysReg;
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/** The old physical register that the arch. register was renamed to. */
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PhysRegIndex prevPhysReg;
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};
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/** A per-thread list of all destination register renames, used to either
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* undo rename mappings or free old physical registers.
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*/
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std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
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/** Pointer to CPU. */
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O3CPU *cpu;
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/** Pointer to main time buffer used for backwards communication. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get IEW's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write infromation heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toDecode;
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/** Rename instruction queue. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to write any information heading to IEW. */
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typename TimeBuffer<RenameStruct>::wire toIEW;
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/** Decode instruction queue interface. */
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TimeBuffer<DecodeStruct> *decodeQueue;
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/** Wire to get decode's output from decode queue. */
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typename TimeBuffer<DecodeStruct>::wire fromDecode;
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/** Queue of all instructions coming from decode this cycle. */
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InstQueue insts[Impl::MaxThreads];
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/** Skid buffer between rename and decode. */
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InstQueue skidBuffer[Impl::MaxThreads];
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/** Rename map interface. */
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RenameMap *renameMap[Impl::MaxThreads];
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/** Free list interface. */
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FreeList *freeList;
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/** Pointer to the list of active threads. */
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std::list<ThreadID> *activeThreads;
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/** Pointer to the scoreboard. */
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Scoreboard *scoreboard;
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/** Count of instructions in progress that have been sent off to the IQ
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* and ROB, but are not yet included in their occupancy counts.
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*/
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int instsInProgress[Impl::MaxThreads];
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/** Count of Load instructions in progress that have been sent off to the IQ
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* and ROB, but are not yet included in their occupancy counts.
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*/
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int loadsInProgress[Impl::MaxThreads];
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/** Count of Store instructions in progress that have been sent off to the IQ
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* and ROB, but are not yet included in their occupancy counts.
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*/
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int storesInProgress[Impl::MaxThreads];
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/** Variable that tracks if decode has written to the time buffer this
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* cycle. Used to tell CPU if there is activity this cycle.
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*/
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bool wroteToTimeBuffer;
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/** Structures whose free entries impact the amount of instructions that
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* can be renamed.
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*/
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struct FreeEntries {
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unsigned iqEntries;
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unsigned robEntries;
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unsigned lqEntries;
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unsigned sqEntries;
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};
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/** Per-thread tracking of the number of free entries of back-end
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* structures.
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*/
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FreeEntries freeEntries[Impl::MaxThreads];
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/** Records if the ROB is empty. In SMT mode the ROB may be dynamically
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* partitioned between threads, so the ROB must tell rename when it is
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* empty.
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*/
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bool emptyROB[Impl::MaxThreads];
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/** Source of possible stalls. */
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struct Stalls {
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bool iew;
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bool commit;
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};
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/** Tracks which stages are telling decode to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** The serialize instruction that rename has stalled on. */
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DynInstPtr serializeInst[Impl::MaxThreads];
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/** Records if rename needs to serialize on the next instruction for any
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* thread.
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*/
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bool serializeOnNextInst[Impl::MaxThreads];
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/** Delay between iew and rename, in ticks. */
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int iewToRenameDelay;
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/** Delay between decode and rename, in ticks. */
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int decodeToRenameDelay;
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/** Delay between commit and rename, in ticks. */
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unsigned commitToRenameDelay;
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/** Rename width, in instructions. */
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unsigned renameWidth;
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/** Commit width, in instructions. Used so rename knows how many
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* instructions might have freed registers in the previous cycle.
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*/
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unsigned commitWidth;
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/** The index of the instruction in the time buffer to IEW that rename is
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* currently using.
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*/
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unsigned toIEWIndex;
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/** Whether or not rename needs to block this cycle. */
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bool blockThisCycle;
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/** Whether or not rename needs to resume a serialize instruction
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* after squashing. */
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bool resumeSerialize;
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/** Whether or not rename needs to resume clearing out the skidbuffer
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* after squashing. */
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bool resumeUnblocking;
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/** The number of threads active in rename. */
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ThreadID numThreads;
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/** The maximum skid buffer size. */
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unsigned skidBufferMax;
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PhysRegIndex maxPhysicalRegs;
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/** Enum to record the source of a structure full stall. Can come from
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* either ROB, IQ, LSQ, and it is priortized in that order.
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*/
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enum FullSource {
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ROB,
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IQ,
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LQ,
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SQ,
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NONE
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};
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/** Function used to increment the stat that corresponds to the source of
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* the stall.
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*/
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inline void incrFullStat(const FullSource &source);
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/** Stat for total number of cycles spent squashing. */
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Stats::Scalar renameSquashCycles;
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/** Stat for total number of cycles spent idle. */
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Stats::Scalar renameIdleCycles;
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/** Stat for total number of cycles spent blocking. */
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Stats::Scalar renameBlockCycles;
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/** Stat for total number of cycles spent stalling for a serializing inst. */
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Stats::Scalar renameSerializeStallCycles;
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/** Stat for total number of cycles spent running normally. */
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Stats::Scalar renameRunCycles;
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/** Stat for total number of cycles spent unblocking. */
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Stats::Scalar renameUnblockCycles;
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/** Stat for total number of renamed instructions. */
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Stats::Scalar renameRenamedInsts;
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/** Stat for total number of squashed instructions that rename discards. */
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Stats::Scalar renameSquashedInsts;
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/** Stat for total number of times that the ROB starts a stall in rename. */
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Stats::Scalar renameROBFullEvents;
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/** Stat for total number of times that the IQ starts a stall in rename. */
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Stats::Scalar renameIQFullEvents;
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/** Stat for total number of times that the LQ starts a stall in rename. */
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Stats::Scalar renameLQFullEvents;
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/** Stat for total number of times that the SQ starts a stall in rename. */
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Stats::Scalar renameSQFullEvents;
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/** Stat for total number of times that rename runs out of free registers
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* to use to rename. */
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Stats::Scalar renameFullRegistersEvents;
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/** Stat for total number of renamed destination registers. */
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Stats::Scalar renameRenamedOperands;
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/** Stat for total number of source register rename lookups. */
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Stats::Scalar renameRenameLookups;
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Stats::Scalar intRenameLookups;
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Stats::Scalar fpRenameLookups;
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/** Stat for total number of committed renaming mappings. */
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Stats::Scalar renameCommittedMaps;
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/** Stat for total number of mappings that were undone due to a squash. */
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Stats::Scalar renameUndoneMaps;
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/** Number of serialize instructions handled. */
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Stats::Scalar renamedSerializing;
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/** Number of instructions marked as temporarily serializing. */
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Stats::Scalar renamedTempSerializing;
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/** Number of instructions inserted into skid buffers. */
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Stats::Scalar renameSkidInsts;
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};
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#endif // __CPU_O3_RENAME_HH__
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