5526221847
Restructured rename map and free list to clean up some extraneous code and separate out common code that can be reused across different register classes (int and fp at this point). Both components now consist of a set of Simple* objects that are stand-alone rename map & free list for each class, plus a Unified* object that presents a unified interface across all register classes and then redirects accesses to the appropriate Simple* object as needed. Moved free list initialization to PhysRegFile to better isolate knowledge of physical register index mappings to that class (and remove the need to pass a number of parameters to the free list constructor). Causes a small change to these stats: cpu.rename.int_rename_lookups cpu.rename.fp_rename_lookups because they are now categorized on a per-operand basis rather than a per-instruction basis. That is, an instruction with mixed fp/int/misc operand types will have each operand categorized independently, where previously the lookup was categorized based on the instruction type.
110 lines
4.2 KiB
C++
110 lines
4.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_CPU_POLICY_HH__
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#define __CPU_O3_CPU_POLICY_HH__
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/commit.hh"
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#include "cpu/o3/decode.hh"
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#include "cpu/o3/fetch.hh"
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#include "cpu/o3/free_list.hh"
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#include "cpu/o3/iew.hh"
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#include "cpu/o3/inst_queue.hh"
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#include "cpu/o3/lsq.hh"
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#include "cpu/o3/lsq_unit.hh"
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#include "cpu/o3/mem_dep_unit.hh"
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#include "cpu/o3/regfile.hh"
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#include "cpu/o3/rename.hh"
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#include "cpu/o3/rename_map.hh"
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#include "cpu/o3/rob.hh"
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#include "cpu/o3/store_set.hh"
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/**
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* Struct that defines the key classes to be used by the CPU. All
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* classes use the typedefs defined here to determine what are the
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* classes of the other stages and communication buffers. In order to
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* change a structure such as the IQ, simply change the typedef here
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* to use the desired class instead, and recompile. In order to
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* create a different CPU to be used simultaneously with this one, see
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* the alpha_impl.hh file for instructions.
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*/
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template<class Impl>
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struct SimpleCPUPolicy
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{
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/** Typedef for the freelist of registers. */
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typedef UnifiedFreeList FreeList;
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/** Typedef for the rename map. */
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typedef UnifiedRenameMap RenameMap;
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/** Typedef for the ROB. */
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typedef ::ROB<Impl> ROB;
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/** Typedef for the instruction queue/scheduler. */
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typedef InstructionQueue<Impl> IQ;
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/** Typedef for the memory dependence unit. */
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typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
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/** Typedef for the LSQ. */
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typedef ::LSQ<Impl> LSQ;
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/** Typedef for the thread-specific LSQ units. */
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typedef ::LSQUnit<Impl> LSQUnit;
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/** Typedef for fetch. */
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typedef DefaultFetch<Impl> Fetch;
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/** Typedef for decode. */
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typedef DefaultDecode<Impl> Decode;
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/** Typedef for rename. */
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typedef DefaultRename<Impl> Rename;
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/** Typedef for Issue/Execute/Writeback. */
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typedef DefaultIEW<Impl> IEW;
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/** Typedef for commit. */
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typedef DefaultCommit<Impl> Commit;
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/** The struct for communication between fetch and decode. */
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typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
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/** The struct for communication between decode and rename. */
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typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
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/** The struct for communication between rename and IEW. */
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typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
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/** The struct for communication between IEW and commit. */
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typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
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/** The struct for communication within the IEW stage. */
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typedef ::IssueStruct<Impl> IssueStruct;
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/** The struct for all backwards communication. */
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typedef TimeBufStruct<Impl> TimeStruct;
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};
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#endif //__CPU_O3_CPU_POLICY_HH__
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