22c04190c6
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
103 lines
3 KiB
C++
103 lines
3 KiB
C++
/*
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Timothy M. Jones
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*/
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#ifndef __ARCH_POWER_TYPES_HH__
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#define __ARCH_POWER_TYPES_HH__
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#include "arch/generic/types.hh"
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#include "base/bitunion.hh"
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#include "base/types.hh"
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namespace PowerISA
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{
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typedef uint32_t MachInst;
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BitUnion32(ExtMachInst)
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// Registers
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Bitfield<25, 21> rs;
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Bitfield<20, 16> ra;
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// Shifts and masks
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Bitfield<15, 11> sh;
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Bitfield<10, 6> mb;
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Bitfield< 5, 1> me;
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// Immediate fields
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Bitfield<15, 0> si;
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Bitfield<15, 0> d;
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// Special purpose register identifier
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Bitfield<20, 11> spr;
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Bitfield<25, 2> li;
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Bitfield<1> aa;
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Bitfield<25, 23> bf;
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Bitfield<15, 2> bd;
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Bitfield<25, 21> bo;
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Bitfield<20, 16> bi;
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Bitfield<20, 18> bfa;
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// Record bits
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Bitfield<0> rc31;
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Bitfield<10> oe;
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// Condition register fields
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Bitfield<25, 21> bt;
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Bitfield<20, 16> ba;
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Bitfield<15, 11> bb;
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// FXM field for mtcrf instruction
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Bitfield<19, 12> fxm;
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EndBitUnion(ExtMachInst)
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typedef GenericISA::SimplePCState<MachInst> PCState;
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// typedef uint64_t LargestRead;
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// // Need to use 64 bits to make sure that read requests get handled properly
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// typedef int RegContextParam;
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// typedef int RegContextVal;
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} // PowerISA namespace
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namespace std {
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template<>
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struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const PowerISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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}
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#endif // __ARCH_POWER_TYPES_HH__
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