4709c41d74Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5
Erik Hallnor
2003-10-22 00:23:24 -0400
26ababf2f2Probe is now in. You currently can't probe uncacheable (of course it doesn't make much sense either. Also, probe doesn't currently support compressed data, but will as soon as I encapsulate the calls more.
Erik Hallnor
2003-10-22 00:22:25 -0400
66f115a2dfstatistics.hh: same - bin printing statistics.cc: printing of bins! now all the nice binning functionality is actually useful cuz you can see the data it so nicely took. this prints out only the individual bin values. totals to come. statistics.hh: add a binned() function to each stat so that at print time, we can know if it's binned in order to print it right.
Lisa Hsu
2003-10-21 23:56:31 -0400
a7c88ad2aeMerge zizzer:/bk/m5 into zower.eecs.umich.edu:/z/hsul/bk/clean
Lisa Hsu
2003-10-21 23:18:07 -0400
ede195161bstatistics.hh: fix up some very ambiguous doxygen comments about Formulas
Lisa Hsu
2003-10-21 23:17:55 -0400
c0162074c6Since we don't hand off writebacks anymore, need to actually copy the request when buffering it.
Erik Hallnor
2003-10-21 21:04:22 -0400
adc99b427dI'll fix this screwup with the next change set
Erik Hallnor
2003-10-21 19:22:09 -0400
da1116a11amem_debug.hh: Add debug callout for cache probes. miss_queue.hh, miss_queue.cc, blocking_buffer.hh: Add support for snooping the write buffer. cache.cc: Snoop the Write buffer for writebacks on probes.
Erik Hallnor
2003-10-21 19:19:37 -0400
6bc700e1adMerge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/clean
Erik Hallnor
2003-10-21 19:15:03 -0400
67f6771721When the Bus blocks now it lets the sender know it was a failed transmission. The request stays buffered in the sender, not on the bus like it used to be.
Erik Hallnor
2003-10-21 19:14:54 -0400
f600cff5c2Created new M5 instruction to allow an integer parameter (init_param) to be specified in the INI and then read inside the simulator.
Andrew Schultz
2003-10-21 17:18:17 -0400
ae232a883aMerge zizzer:/bk/m5 into zower.eecs.umich.edu:/z/hsul/bk/clean
Lisa Hsu
2003-10-21 15:45:56 -0400
f600ac613estatistics.hh: change VectorDistProxy name to DistProxy - to be more consistent with other proxy namings.
Lisa Hsu
2003-10-21 15:45:48 -0400
f3d6ac18e8Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5
Erik Hallnor
2003-10-21 01:53:41 -0400
456b9af0c8memtest.cc: Add probe calls to test update probe path.
Erik Hallnor
2003-10-21 01:53:27 -0400
e99c0f901cAdd the probe path to the hierarchy. Two flavors, one updates the location of the block in memory, the other just reads the most up to date data/writes data wherever it is found.
Erik Hallnor
2003-10-21 01:51:59 -0400
02bacb2dfdImplement reset for stats.
Nathan Binkert
2003-10-20 23:08:27 -0400
df488c0e70Clean up callbacks
Nathan Binkert
2003-10-20 21:38:32 -0400
e0b065ff7cSeparate the stuff for SimObject from SimObject builder. This makes testing a bit easier.
Nathan Binkert
2003-10-20 20:17:01 -0400
4963dbf9a9Merge zizzer.eecs.umich.edu:/bk/m5 into crampon.eecs.umich.edu:/z/binkertn/research/m5/latest
Nathan Binkert
2003-10-20 09:23:17 -0400
4489583dfe.del-post-incoming.regression~db4d380a8de2f027: Delete: BitKeeper/triggers/post-incoming.regression
Lisa Hsu
2003-10-20 01:05:07 -0400
2c7a0b87f5simple_cpu.cc: Add data to static memReq and make everything use it. Add init of numLoads.
Erik Hallnor
2003-10-20 00:46:02 -0400
789a2de6f8Check in a first stab at a script to sort the #include lines in a source file. Nate thought this would be cool, and I started on it, but lost interest. I'm mostly committing this so bk stops bugging me about it. Nate, don't start hacking on this until after the ISCA deadline!
Steve Reinhardt
2003-10-19 17:42:51 -0700
f951b00d89Get rid of obsolete code, most of it '#if 0'ed anyway. Mostly vestiges of Dave's long-gone instruction prefetching stuff.
Steve Reinhardt
2003-10-19 17:30:26 -0700
2f37dd455aMerge zizzer.eecs.umich.edu:/bk/m5 into crampon.eecs.umich.edu:/z/binkertn/research/m5/latest
Nathan Binkert
2003-10-19 05:50:53 -0400
83d32482dcAdd comment to elaborate on store-conditional result code (and remove stale reference to machine.def).
Steve Reinhardt
2003-10-18 21:21:14 -0700
ba12dee914Get rid of GZIP_PATH
Nathan Binkert
2003-10-18 08:55:07 -0400
1bebc1ab2fMerge ehallnor@zizzer:/bk/m5 into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
Erik Hallnor
2003-10-17 17:51:15 -0400
eec404abe6Add FALRU stats, tweak doxygen configs a bit.
Erik Hallnor
2003-10-17 17:51:08 -0400
24a1ee1ac5Accidentally ran my delete whitespace program on decoder.cc regenerate a decoder.cc from the isa_desc
Nathan Binkert
2003-10-17 15:35:50 -0400
73f78b9587Add a README for the release. Ideally we would move this up a level (to the top-level release dir) before shipping it.
Steve Reinhardt
2003-10-17 09:32:00 -0700
73c1802f7aUpdates to doxygen config files.
Steve Reinhardt
2003-10-17 07:41:25 -0700
c093f29f6bClear up the last of the Doxygen warnings
Erik Hallnor
2003-10-16 17:56:16 -0400
aeaf133d27Merge ehallnor@zizzer:/bk/m5 into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
Erik Hallnor
2003-10-16 17:04:25 -0400
4134477369Add a commited loads event queue similar to the one for commited instructions. Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.
Erik Hallnor
2003-10-16 17:04:18 -0400
ea5dc1d5dfAdded to new doxygen configs (posting internally and externally). Changed the default to not use dot to speed testing of documentation for warnings. We probably don't want to release postint and postext since there is information about absolute file locations in them.
Erik Hallnor
2003-10-16 17:02:14 -0400
a6788d64ddMerge stever@zizzer:/bk/m5 into vm1.vmnet.nat:/z/stever/bk/m5
Steve Reinhardt
2003-10-16 12:41:50 -0700
8b4f16a727Minor documentation tweaks.
Steve Reinhardt
2003-10-16 12:41:35 -0700
cd22503edapost-incoming.regression: dirname in this repo too
Lisa Hsu
2003-10-16 15:28:40 -0400
5e7f7a268dpost-incoming.regression: added log info
Lisa Hsu
2003-10-16 09:39:08 -0400
323306795epost-incoming.regression: finally, the right one. so simple, yet path so heinous.
Lisa Hsu
2003-10-16 09:23:48 -0400
5ebda9ef2cDon't chmod generated source files because bitkeeper just complains too much.
Nathan Binkert
2003-10-16 00:06:29 -0400
5a361bfe4ddisable the post-incoming.regression for now
Nathan Binkert
2003-10-15 23:56:13 -0400
d9d3d9af54fix another bug
Nathan Binkert
2003-10-15 23:51:43 -0400
7c8a97b8earemove a newline
Nathan Binkert
2003-10-15 23:48:41 -0400
6e6bc57088Merge ehallnor@zizzer:/bk/m5 into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
Erik Hallnor
2003-10-15 23:08:52 -0400
9429297274Set the default number of write buffers to 8, add write_buffer param to cache to specify it.
Erik Hallnor
2003-10-15 23:07:32 -0400
7315c32058post-incoming.regression: use the correct operator
Nathan Binkert
2003-10-15 22:12:56 -0400
1d9e047397footer.html: removed blank line
Lisa Hsu
2003-10-15 20:49:12 -0400
69143668adpost-incoming.regression: lost an i, hehe, in cut and paste
Lisa Hsu
2003-10-15 20:47:51 -0400
b9362e4b6ffooter.html: added blank space
Lisa Hsu
2003-10-15 20:45:11 -0400
c0c79399fapost-incoming.regression: new file
Lisa Hsu
2003-10-15 20:41:55 -0400
1f3f180b95Need to cast to avoid infinite recursion.
Erik Hallnor
2003-10-15 17:36:10 -0400
11eaf2f2abRemove conflicts
Erik Hallnor
2003-10-15 17:17:19 -0400
4159dc218aAdd a stat to track the cycle when the cache has all blocks touched (if ever).
Erik Hallnor
2003-10-15 17:11:46 -0400
f96032235eFix the default target for the makefile
Nathan Binkert
2003-10-15 16:42:53 -0400
8dd080032bGlobal whitespace fixes Mainly removing whitespace at the end of lines. This will reduce future diffs/conflicts. Also adding a space after if, while, and for
Nathan Binkert
2003-10-15 16:39:37 -0400
1e71e6b748Fix up the targetarch target so that things build a little better. This changes how the setup script works, but you don't need to re-run setup.
Nathan Binkert
2003-10-15 16:22:50 -0400
722f9bc3c8Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5 into zans.eecs.umich.edu:/z/binkertn/research/m5/latest
Nathan Binkert
2003-10-14 18:04:28 -0400
f8d850195btry to get everything to compile correctly again
Nathan Binkert
2003-10-14 18:04:20 -0400
acf025a463Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/y/sraasch/m5
Steve Raasch
2003-10-14 17:06:05 -0400
8be145a42fFixes for the new stats in SegmentedIQ
Steve Raasch
2003-10-14 17:05:42 -0400
2ac3dc5aa1Fix to test change. Will update tests once KERNEL compiles again. The only test change that is real is SIM:cycle is now gone.
Erik Hallnor
2003-10-14 15:01:28 -0400
7755f825d4Merge ehallnor@zizzer:/bk/m5 into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
Erik Hallnor
2003-10-14 13:29:20 -0400
118f5da7f8hostinfo.cc: Trial fix, uint64_T > long
Erik Hallnor
2003-10-14 13:29:12 -0400
9d51e99865Use common trigger script for email.
Steve Reinhardt
2003-10-14 12:55:49 -0400
4759c203c7Remove all of the Tru64 specific stuff from the base System object into its own Tru64System object. Also remove the System builder stuff and create a Tru64System builder. This makes it much simpler to support more operating systems.
Nathan Binkert
2003-10-14 12:19:59 -0400
459fe3f094config: Make /m5/latest read-only as well.
Steve Reinhardt
2003-10-14 11:37:30 -0400
1a12f365e0Fix trigger-happy triggers.
Steve Reinhardt
2003-10-14 01:47:40 -0400
fd55a1cbbbgeneric: Only run on incoming pushes
Steve Reinhardt
2003-10-14 01:36:59 -0400
ea8fa86e10Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
Steve Reinhardt
2003-10-13 22:22:20 -0700
e6e1c27343Fix for cpu.cc -> full_cpu.cc rename.
Steve Reinhardt
2003-10-13 22:21:49 -0700
af5cdc1d8cRename CPU object to FullCPU
Steve Reinhardt
2003-10-13 22:21:19 -0700
af35f423baSince I seem to be bug compatible with the head I'm going to commit. There is still one documentation warning in the stat code, probably a doxygen error.
Erik Hallnor
2003-10-14 01:20:26 -0400
35e5d907c4Update generated files. We need to fix the permissions issues here.
Steve Reinhardt
2003-10-13 21:55:43 -0700
00f8ea4576Another case where we need to fix an include path for a generated file in the script that generates it.
Steve Reinhardt
2003-10-13 21:52:42 -0700
75e5460579Rename full_cpu/cpu.cc,hh to full_cpu.cc,hh.
Steve Reinhardt
2003-10-13 21:51:34 -0700
1348e57ac1Fix up decoder.cc generation... this got broken at the directory reorg.
Steve Reinhardt
2003-10-13 21:47:27 -0700
4dbe897b15Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
Steve Reinhardt
2003-10-13 21:00:52 -0700
551e67d3d6Read-only checkout in root repository.
Steve Reinhardt
2003-10-13 23:52:57 -0400
a246f5d757Commit trigger files
Steve Reinhardt
2003-10-13 23:29:46 -0400
8f1855034eMerge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
Steve Reinhardt
2003-10-13 19:54:11 -0700
60a7bd950bCopyData and CopyString moved from kernel.cc to vtophys.cc kernel.cc and kernel.hh moved to kern/tru64
Nathan Binkert
2003-10-13 16:09:33 -0400
7646a5a1e0Add m5 emacs style file.
Steve Reinhardt
2003-10-13 08:04:38 -0700
b177f696ffTry to get the correct license on various files remove stuff that is ambiguous Clean up code a bit
Nathan Binkert
2003-10-13 02:00:47 -0400
940c214759Pisa is way out of date. Whack it for now. Hopefully someone will resurrect it some day.
Nathan Binkert
2003-10-12 22:22:29 -0400
94955d1221Get rid of obsolete sim/cache directory.
Steve Reinhardt
2003-10-11 21:51:14 -0700
7d64ac98d5get rid of implicit rules
Nathan Binkert
2003-10-11 00:35:06 -0400
025ab84ed7Merge ehallnor@zizzer:/bk/m5 into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
Erik Hallnor
2003-10-10 23:23:44 -0400
d6a5a622a5Fully Document Statistics::Detail::Stat. More to follow.
Erik Hallnor
2003-10-10 23:23:30 -0400
b61ec9773aMake things work on OpenBSD again
Nathan Binkert
2003-10-10 22:59:51 -0400
6770411543fix includes
Nathan Binkert
2003-10-10 21:17:06 -0400
dfd15ec34aMerge zizzer:/bk/m5 into zower.eecs.umich.edu:/z/hsul/bk/m5
Lisa Hsu
2003-10-10 15:59:51 -0400
86c8eb7b9fstatistics.hh: Grouped the Visible Stats Types and commented them.
Lisa Hsu
2003-10-10 15:58:56 -0400
3d55a263fdThis is a utility.
Nathan Binkert
2003-10-10 15:09:25 -0400