Commit graph

3606 commits

Author SHA1 Message Date
Kevin Lim
5ec58c4bdc Fix up some ISA related stuff.
arch/alpha/isa/decoder.isa:
    Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
    Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.

--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae
2006-08-02 12:07:44 -04:00
Kevin Lim
5be592f870 Make checker handle not executing the same instruction as the main CPU a little better.
Also add the option for the checker to update itself with the main CPU's state if it executes an instruction differently (so it will handle DMA timing errors properly).

--HG--
extra : convert_revision : 760d11ec1a249bc75e2807d320866b5d08c2b6f2
2006-08-02 12:06:59 -04:00
Kevin Lim
cbfbb7bc56 Updates to bring CPU portion of m5 up-to-date with newmem.
--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4
2006-08-02 12:05:34 -04:00
Kevin Lim
8d220c5c10 Updates for registers and stuff.
arch/alpha/ev5.cc:
    Update for copying IPRs.
arch/alpha/isa_traits.hh:
    Allow for misc register file to serialize.  Also add some register copying code.
cpu/cpu_exec_context.cc:
    Use ISA's function to copy registers.

--HG--
extra : convert_revision : 09fa3b2b1b229cbf3a34f69354953da2607c2a8f
2006-08-02 12:04:18 -04:00
Kevin Lim
db6c908e0f Minor configuration updates.
--HG--
extra : convert_revision : d638d440edd91caa31977eb6d2325c899962936f
2006-08-02 11:56:06 -04:00
Kevin Lim
08c0919b43 Clean up some more config stuff.
configs/common/FSConfig.py:
    Clean up some code to make functions look less like classes.  Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
    Update for changed code.
src/python/m5/__init__.py:
    Put makeList into m5.

--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
2006-07-27 17:49:00 -04:00
Kevin Lim
53e17d0368 Update ref stats.
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/stderr:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/stdout:
    Updated output.

--HG--
extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 17:47:43 -04:00
Kevin Lim
94dd369fcd Output the command line.
src/python/m5/main.py:
    Output the command line being used.

--HG--
extra : convert_revision : 51dadb0ef79ca1e8bbb5a3bd64110071c30ade0d
2006-07-27 17:37:28 -04:00
Kevin Lim
52c3991182 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 70221af596bddbfcc40646d03f175ef5e4b75909
2006-07-27 16:43:29 -04:00
Kevin Lim
64b7213046 Need config read/write latency.
--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
2006-07-27 16:43:02 -04:00
Korey Sewell
95561dc138 MIPS ISA runs 'hello world' in O3CPU ...
src/arch/mips/isa/base.isa:
    special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
    add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
    Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
    Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
    Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
    change comment

--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
2006-07-26 18:47:06 -04:00
Gabe Black
36e9ca5611 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 3bb2cdd9b286e7f0235fb5fd5099b89775e05a10
2006-07-26 03:48:48 -04:00
Gabe Black
e803c8a912 Added alot of fp instructions, and some impdep instructions.
--HG--
extra : convert_revision : cc703919b59e674044ae370a65dc03deece6d69e
2006-07-26 03:42:16 -04:00
Gabe Black
e081615cd9 Now ignore sigaction
src/arch/sparc/isa/operands.isa:
    Added the GSR register as a control register

--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
2006-07-26 03:40:56 -04:00
Korey Sewell
6e969c31c7 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
2006-07-23 13:41:53 -04:00
Korey Sewell
19ca97af79 This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!

Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )

src/arch/alpha/isa/mem.isa:
    spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
    Gabe really authored this
src/arch/mips/isa/decoder.isa:
    add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
    Steven really did this file
src/arch/mips/isa/formats/branch.isa:
    fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
    Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
    update LoadStoreBase template
src/arch/mips/isa_traits.cc:
    update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
    no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
    add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
    add in nextNPC variable and supporting functions.

    add isCondDelaySlot function

    Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
    init nextNPC
src/cpu/o3/SConscript:
    add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
    no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
    Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
    add some extra communication variables to aid in handling the
    delay slots
src/cpu/o3/commit.hh:
    minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
    Update function interface ...

    adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
    update removeInstsNotInROB
src/cpu/o3/decode.hh:
    declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
    Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
    declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
    no need for my name here
src/cpu/o3/isa_specific.hh:
    add in MIPS files
src/cpu/o3/scoreboard.hh:
    dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
    no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
    add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
    MIPS file for O3CPU...mirrors ALPHA definition

--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
2006-07-23 13:39:42 -04:00
Gabe Black
887e00f18d Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : f6a68bbf8aad9be54ff24310b3e51eaed9abb8b5
2006-07-23 03:06:12 -04:00
Gabe Black
8711078885 Added myself to the authors list.
--HG--
extra : convert_revision : d90154159473ed93c5b50cf3221e132eda242852
2006-07-23 03:04:46 -04:00
Kevin Lim
f9729e999f Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 45650c90385b4e13e79ccf271a30bb55552b380f
2006-07-23 00:10:52 -04:00
Kevin Lim
6ef6e9b14d Fix up test.py
configs/test/test.py:
    Fix up this config.

--HG--
extra : convert_revision : e15071ee27b860cc3ad79277aa61f3e6bb7405d3
2006-07-23 00:10:11 -04:00
Gabe Black
c77cb31473 Reorganized SPARC binaries
--HG--
rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc
extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22 17:30:50 -04:00
Gabe Black
14b11a9734 Fixed subtract with carry, and started some work with floating point.
src/arch/sparc/isa/decoder.isa:
    fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
    Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
    Fixed some memory errors related to floating point.

--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
2006-07-22 15:50:40 -04:00
Kevin Lim
7ccdb7accc Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
    Make test CPUs option non-sticky.
configs/common/FSConfig.py:
    Be sure to set the memory mode.
configs/test/fs.py:
    Wrong string.
tests/SConscript:
    Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
    Update output.

--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-22 15:50:39 -04:00
Kevin Lim
db5f710a7b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
    Hand merge.

--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21 16:08:17 -04:00
Kevin Lim
a6c2e5cca0 Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
    Pull out a lot of common code and put it into configs/common/FSConfig.py.

--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21 15:56:35 -04:00
Kevin Lim
acf9cf21a2 Missed some files in a previous check-in. Also check-in the SMT tests. Reference stats will be coming soon.
--HG--
extra : convert_revision : c2f7ea613f350e62395f2b50e4c8cc21c6960a22
2006-07-21 15:53:07 -04:00
Kevin Lim
bf90e1dbde Minor functionality updates.
SConstruct:
    Include an option to specify the CPUs being tested.
src/cpu/SConscript:
    Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
    Include default options.  Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
    Several minor updates (sorry for one commit).  Updated the copyright and fixed some m5 style issues.  Also added the ability to specify which CPUs to run the tests on.

--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
2006-07-21 15:46:12 -04:00
Kevin Lim
bd33d8d4ac Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.
--HG--
rename : configs/test/SysPaths.py => configs/common/SysPaths.py
extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-21 15:42:44 -04:00
Gabe Black
8bbe925192 Fixed a glitch in the disassembly output.
--HG--
extra : convert_revision : 833aa358b12ac987e0ab467708425c17e5a8fdb7
2006-07-20 21:01:57 -04:00
Gabe Black
419acd31cb Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 0c696374b19b27c0bd50ffa7f75117b1e211e4bc
2006-07-20 19:04:09 -04:00
Ali Saidi
0850c3dedb Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c7fedc68996f2f6cbfb70baebf7c87e0736da883
2006-07-20 19:04:08 -04:00
Ali Saidi
851f91f245 Move PioPort timing code into Simple Timing Port object
Make PioPort use it
Make Physical memory use it as well

src/SConscript:
    Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
    Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
    use a simple timing port stuff instead of rolling our own here

--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
2006-07-20 19:03:47 -04:00
Ali Saidi
e8a3295075 Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz

configs/test/fs.py:
    Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Enforce the timing cpu ticking at it's clock rate

--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-20 19:00:40 -04:00
Ali Saidi
15e5ce96c7 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 8c747208d72ffbb0160a2ad4a75383420debdf83
2006-07-19 17:59:04 -04:00
Ali Saidi
6175f712b3 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c5dbee4ba46fae1edba732f4bd05ef984a46d088
2006-07-19 17:24:45 -04:00
Ali Saidi
a50c5cc999 Change the device latency here to a latency rather than a Tick
src/python/m5/objects/Device.py:
src/python/m5/objects/Pci.py:
    Change the default here to a latency rather than a Tick

--HG--
extra : convert_revision : b9366dd89646cea27a836baf249ac2da38c1809f
2006-07-19 17:24:20 -04:00
Kevin Lim
87d4859458 Minor changes to reflect state used for regression stats.
src/cpu/checker/cpu.hh:
    Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
    Set default clock to 1 THz.

--HG--
extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
2006-07-19 16:09:34 -04:00
Kevin Lim
4bd025742d Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model>
Right now only non-SMT SE regression tests have been added back in.  The rest are pending getting SMT working, and consolidating the FS configuration files.

Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.

Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work.  The test itself should probably work once the code is fixed.

SConstruct:
    Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
    Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.

--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
2006-07-19 16:07:25 -04:00
Kevin Lim
660ea2b176 Get the path to load the ini file from. I'm not sure if this fix is needed in other places as well.
src/sim/main.cc:
    Get the path to load the ini file from.

--HG--
extra : convert_revision : aa38fc9b1bc99cd74d095cbfc67253e4549f91d3
2006-07-19 15:28:53 -04:00
Kevin Lim
85515c4976 O3CPU fixes.
src/cpu/o3/lsq_unit.hh:
    LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
    LSQ needs to decrement the WB counter if the load is squashed.

--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
2006-07-19 15:28:02 -04:00
Kevin Lim
0cedb23d3c Some minor compiling fixes.
src/cpu/o3/iew.hh:
    Non-debug compile fixes.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
    Merge fix.

--HG--
extra : convert_revision : 38081925d2b74d8f64acdb65dba94b2bf465b16a
2006-07-19 15:26:48 -04:00
Kevin Lim
1fdf14dd5a Update configs.
configs/test/test.py:
    Update for changes to SEConfig.

--HG--
extra : convert_revision : a089a7db4035889db01d543d9a18ea6526f832ca
2006-07-19 15:24:22 -04:00
Kevin Lim
82b1a278ec Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 06cb509fbbce882793997db275ff7c54058ae619
2006-07-19 14:46:05 -04:00
Gabe Black
b7b603f9a7 Cleaned things up a little.
--HG--
extra : convert_revision : 7091b0d02e5b7c80be43b5ab1ac003dc89c4c136
2006-07-19 02:07:00 -04:00
Gabe Black
44974a4462 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 516c357f98c7a571c70362babd3fa162fbc2ed5a
2006-07-18 18:23:23 -04:00
Korey Sewell
fe9e851e8c update test3
--HG--
extra : convert_revision : e41feeee87d1da348604a37f7349900dcbd3a4d9
2006-07-17 16:50:20 -04:00
Kevin Lim
31ac8e7337 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
    SCCS merged

--HG--
extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-14 17:54:43 -04:00
Kevin Lim
138a4faf28 Minor updates.
src/python/m5/config.py:
    Formatting.
src/python/m5/main.py:
    Slightly more useful output when you don't enter in a valid script file.

--HG--
extra : convert_revision : 5a71a6c94dbedeb000f83f57b0b575c2df924509
2006-07-14 17:53:16 -04:00
Kevin Lim
40ebf0811a Fix the CheckerCPU being included via python.
src/arch/SConscript:
    Fixes for including the CheckerCPU if it's specified via command line.  Previously the env variable was actually being modified.
src/cpu/SConscript:
    Copy the CPU_MODELS from the env, don't create a proxy to it.

--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
2006-07-14 17:51:29 -04:00
Korey Sewell
07186de5a1 forgot tid
--HG--
extra : convert_revision : 272ef8f9cd0802770edc4dcef2c26dc44de71e47
2006-07-14 13:22:35 -04:00