Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
src/mem/packet.cc:
Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
Fix for the proper semantics of fixPacket
--HG--
extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
Make PioPort use it
Make Physical memory use it as well
src/SConscript:
Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
use a simple timing port stuff instead of rolling our own here
--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
