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Author	SHA1	Message	Date
Steve Reinhardt	f0c05de9f9	Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem ... into zizzer.eecs.umich.edu:/z/stever/bk/newmem-py --HG-- extra : convert_revision : 36640569d33c4410320b8444bb572f408bf5edde	2006-05-30 19:45:54 -04:00
Steve Reinhardt	e371dc32a9	Clean up Python embedding to build on zizzer (where python2.4 ... is currently in /usr/local instead of /usr). SConstruct: Use information from the Python interpreter used to run scons to find the version & paths for include & library files. This means that linking with a different interpreter requires invoking scons with that interpreter... add comment to that effect. src/sim/main.cc: Check return codes of Python interpreter calls for errors. Get rid of include of obsolete header. --HG-- extra : convert_revision : 90916bd8690fe1e6c9afdb0dfa1aa0d352a73a46	2006-05-30 19:44:57 -04:00
Ali Saidi	aa11330ddb	Merge zizzer:/bk/newmem ... into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4b7ba74eebe9b8370a12f8eb9905f83e2f380585	2006-05-30 18:57:53 -04:00
Ali Saidi	09d8a1e125	Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since ... it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true) Removed Port Blocked/Unblocked and replaced with sendRetry(). Remove possibility of packet mangling if packet is going to be refused anyway in bridge src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true) src/dev/io_device.cc: src/dev/io_device.hh: Make DMA Timing requests/responses work. Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true) src/mem/bridge.cc: src/mem/bridge.hh: Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true) Removed Port Blocked/Unblocked and replaced with sendRetry(). Remove posibility of packet mangling if packet is going to be refused anyway. src/mem/bus.cc: src/mem/bus.hh: Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then src/mem/port.hh: Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true) Removed Blocked/Unblocked port status, their functionality is really duplicated in the recvRetry() method --HG-- extra : convert_revision : fab613404be54bfa7a4c67572bae7b559169e573	2006-05-30 18:57:42 -04:00
Kevin Lim	4a5b51b516	Merge ktlim@zizzer:/bk/m5 ... into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges. --HG-- rename : build/SConstruct => SConstruct rename : SConscript => src/SConscript rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa rename : base/traceflags.py => src/base/traceflags.py rename : cpu/SConscript => src/cpu/SConscript rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh rename : cpu/cpu_models.py => src/cpu/cpu_models.py rename : cpu/exec_context.hh => src/cpu/exec_context.hh rename : cpu/exetrace.cc => src/cpu/exetrace.cc rename : cpu/exetrace.hh => src/cpu/exetrace.hh rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/static_inst.hh => src/cpu/static_inst.hh rename : kern/system_events.cc => src/kern/system_events.cc rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc extra : convert_revision : ff351fc0e3a7c0f23e59fdbec33d8209eb9280be	2006-05-30 14:17:41 -04:00
Steve Reinhardt	0337db3388	Link in Python interpreter. ... Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029	2006-05-30 13:11:34 -04:00
Steve Reinhardt	d308055afc	Fix SCons version check. ... SConstruct: Handle SCons version check error when running on SCons 0.96 and previous. --HG-- extra : convert_revision : 37595a468a9b56336c3f88a1057706f89bee9157	2006-05-30 06:34:26 -04:00
Ali Saidi	e60dc5195c	commit a couple of minor things that I forgot to last time. ... src/SConscript: src/arch/sparc/SConscript: commit a couple of things that I forgot to last time. --HG-- extra : convert_revision : f140912905b9d36eccc27e35ebcaf2c15611b56b	2006-05-29 18:25:02 -04:00
Ali Saidi	c0cf76c837	Create a new CpuEvent class that has a pointer to an execution context in the object and places itself on a global list so ... so the events can be migrated on cpu switches. Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc parameter Use new CpuEventWrapper class from tick compare events on sparc src/arch/sparc/regfile.hh: Use new CpuEventWrapper class from tick compare events src/arch/sparc/ua2005.cc: Move definition to to a fullsystem only file, since it is. src/cpu/base.cc: On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs. --HG-- extra : convert_revision : eecf4540427cc0ddf75e19a3371cf32b56cba0f5	2006-05-29 18:24:27 -04:00
Ali Saidi	dc29a7c8ae	split off fullsystem and se iprs into two functions to remove lots of #ifs ... setup all initialization stuff for UA2005 Setup fullsys build options Start to make fullsystem compile src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: RCS to BitKeeper src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add support for doing virtual to physical translation using the in-memory page table src/arch/sparc/vtophys.cc: a tad bit of error checking src/arch/sparc/vtophys.hh: Cleanup of full-system global variables, primarily in simple_cpu.cc, to allow multi-system simulations. (Multiple systems not yet yested though.) Also changes to build sim_smt in full-system mode (though with only SimpleCPU and not the full timing CPU for now). Still to do: minimize changes in SimpleCPU code between full-system and application modes... way too many ifdefs there. Much of the full-system stuff moved into SimpleCPU should be put in a new System object to allow multiprocessor simulations. Converted last remaining modules from C to C++ (mostly in /old). Renamed all .c files to .cc and a few .h files to .hh. Renamed architecture-specific files in arch/$TARGET from $TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless intermediate files in object directory. Split exo-specific definitions out of machine.hh into machine_exo.h. Specifics: In machine.def, null resource descriptors must be FUClamd_NA (and not NA) to pass C++ type checking. Enhanced error checking/reporting in bas src/arch/sparc/vtophys.cc: - Get rid of my String class, the Vector class, the bitvector class, and my doubly linked list class. - Convert tokenize, to_number (formerly StringToNumber) and eat_white to function on stl strings. - Change most cases of char * and const char * to string, or const string & - Some formatting and style nits, but not too many. src/arch/sparc/vtophys.cc: simplify src/arch/sparc/vtophys.cc: Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read & write, overloaded on the type of the 'data' argument. Merged the full-system and non-full-system implementations of these eight original functions into two common template functions. To support this, also renamed (read|write)[1248] on memory_object and derivatives to just read & write, again overloaded on the type of the 'data' argument. Many of these functions could now be condensed into a few template functions (though with a level of indirection so that the interface can remain virtual). I did not do that though. src/arch/sparc/vtophys.cc: First pass at compiling with gcc 3.x. Lots of "std::" in header files, "using namespace std" in source files. (Note policy of not putting "using" statements in headers or before includes in sources.) Still not able to compile with gcc 3.2. Errors: - Can't create an ifstream from a file descriptor anymore (breaks IniFile). - "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc: not clear why since it's in the public part of the class declaration. - cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ? SimObjectParam<PipeTrace*>& : int' operator") - pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'" Warnings: - strstream now deprecated... needs some rewriting in sat_counter.hh and hybrid_pred.hh (need to get all that code out of the headers anyway) - trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not give a valid preprocessing token' - major "implicit typename" issues in base/sized.hh src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Implement some interval statistics for full system mode. Create a callpal function that is called when a callpal occurs so it's easier to manipulate the statics. Rework the vtophys stuff to make it a bit cleaner. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Get rid of almost all old-style object names. This commit is equivalent to running the following script on the current head: #! /bin/sh find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\ s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\ s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\ s/\bmain_memory\b(?!\.hh)/MainMemory/g;\ s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\ s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\ s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\ s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\ s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\ s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\ s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\ s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\ s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\ s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\ s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\ s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\ s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\ s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \; src/arch/sparc/vtophys.cc: since cprintf properly deals with 64-bit types, stop using FMT* as much as possible src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Change byte_t etc. to C99 standard int8_t etc. Other than old/host.h, all other changes were produced by this script: #! /bin/sh find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\ s/\bbyte_t\b(?!\.hh)/uint8_t/g;\ s/\bsbyte_t\b(?!\.hh)/int8_t/g;\ s/\bhalf_t\b(?!\.hh)/uint16_t/g;\ s/\bshalf_t\b(?!\.hh)/int16_t/g;\ s/\bword_t\b(?!\.hh)/uint32_t/g;\ s/\bsword_t\b(?!\.hh)/int32_t/g;\ s/\bqword_t\b(?!\.hh)/uint64_t/g;\ s/\bsqword_t\b(?!\.hh)/int64_t/g;\ s/\bbool_t\b(?!\.hh)/bool/g;\ s/\bdfloat_t\b(?!\.hh)/double/g;\ s/\bsfloat_t\b(?!\.hh)/float/g;' {} \; src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add CVS Id tags src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Massive renaming to (almost) eliminate all md_* and MD_* names in preparation for total exorcism of machine.def. Most of the changes in this commit were performed with the following perl script (perl -pi <script> <files>). A small amount of manual fixup was needed to (mostly getting rid of the Addr typedefs in the various memory objects now that the former md_addr_t has that name). # rename machine-dependent types and constants (will be moving into ISA traits object) s/md_addr_t/Addr/g; s/md_intreg_t/IntReg/g; s/md_gpr_t/IntRegFile/g; s/md_fpreg_t/FloatReg/g; s/md_fpr_t/FloatRegFile/g; s/md_ctrlreg_t/MiscReg/g; s/md_ctrl_t/MiscRegFile/g; s/md_ipr_t/InternalProcReg/g; s/md_anyreg_t/AnyReg/g; s/md_inst_t/MachInst/g; s/regs_t/RegFile/g; # manually fix declaration in old/regs.h and a few forward decls s/struct RegFile/RegFile/g; s/MD_NUM_IREGS/NumIntRegs/g; s/MD_NUM_FREGS/NumFloatRegs/g; s/MD_NUM_CREGS/NumMiscRegs/g; s/MD_IPR_NUM/NumInternalProcRegs/g; s/MD_TOTAL_REGS/TotalNumRegs/g; s/MD_REG_ZERO/ZeroReg/g; src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: New ISA description system. No more machine.def! Instructions are now decoded into StaticInst objects, and all static instruction properties (including execution behavior) are associated with those objects. Extended documentation in progress. Currently supports Alpha only; PISA will not compile. Use END_OF_MACHINE_DOT_DEF tag to extract previous version. src/arch/sparc/vtophys.cc: get rid of MD_IPR_foo and call it IPR_foo add some comments to describe what the various PALtemp registers do formatting src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: license src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: a little style src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add attribution to license. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Make include paths explicit. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: CopyData and CopyString moved from kernel.cc to vtophys.cc kernel.cc and kernel.hh moved to kern/tru64 src/arch/sparc/vtophys.hh: Include isa_traits.hh for Addr src/arch/sparc/vtophys.cc: formatting fixes src/arch/sparc/vtophys.cc: fix up vtophys to deal with translations if there is no ptbr, and to deal with PAL addresses add ptomem which is just a wrapper for dma_addr src/arch/sparc/vtophys.hh: add ptomem which is a wrapper for dma_addr with the same usage as vtomem src/arch/sparc/vtophys.cc: Fix to remote debugger while in PAL code src/arch/sparc/vtophys.cc: Remote an old hack that is now unnecessary src/arch/sparc/vtophys.cc: Removed buggy code that tries to fix PAL addresses (may cause problems while trying to debug in PAL code, but that should do this fix outside of vtophys) src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Updated Copyright src/arch/sparc/vtophys.cc: added back some code andrew removed and couldn't remember why. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: rename CopyData to CopyOut and implement CopyIn to copy data from the simulator into the simulatee src/arch/sparc/vtophys.cc: fixed a bad merge from linux<->tru64 src/arch/sparc/vtophys.cc: Check max address pal can be at so we don't do the wrong conversion if gdb asks for an unaligned access. src/arch/sparc/vtophys.cc: PGOFSET -> ALPHA_PGOFSET to avoid include file problems src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: in the arch/alpha directory we should use arch/alpha, not targetarch. sort includes while we're here. src/arch/sparc/vtophys.cc: use new constants, functions and structs to clean up the vtophys code. src/arch/sparc/vtophys.hh: Clean up a little bit and make the protypes match new changes. src/arch/sparc/vtophys.cc: deal with isa addition src/arch/sparc/vtophys.cc: shuffle files around for new directory structure src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Remove RCS Id string src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Update copyright dates and author list src/arch/sparc/vtophys.cc: Added a using directive for AlphaISA src/arch/sparc/vtophys.hh: Added the AlphaISA namespace specifier where needed src/arch/sparc/vtophys.hh: Made Addr a global type src/arch/sparc/vtophys.cc: Change access to the IPR to go through the XC. src/arch/sparc/vtophys.cc: Avoid directly accessing objects within the XC. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: fixed for new memory system put in namespace AlphaISA src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: Remove authors from copyright. src/arch/sparc/vtophys.cc: bk cp alpha/vtophys.cc sparc/vtophys.cc src/arch/sparc/vtophys.hh: bk cp alpha/vtophys.hh sparc/vtophys.hh src/arch/sparc/SConscript: remove fullsystem files that don't exist src/arch/sparc/isa_traits.hh: split off fullsystem and se iprs into two functions to remove lots of #ifs src/arch/sparc/regfile.hh: split off fullsystem and se iprs into two functions to remove lots of #ifs setup all initialization stuff for UA2005 src/arch/sparc/system.cc: src/arch/sparc/system.hh: Add system level tick storage to make stick be syncronized across multiple processors src/arch/sparc/vtophys.hh: start to create a vtophys for Sparc src/base/loader/symtab.hh: Addr is defined in sim/host.hh --HG-- extra : convert_revision : ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d	2006-05-29 16:53:47 -04:00
Gabe Black	4b855592eb	Added in the IprAccessOp flag for priveleged and hyperpriveleged instructions. ... --HG-- extra : convert_revision : a53297d595e5efd094a5978f4d3afde2c603d109	2006-05-29 00:02:44 -04:00
Gabe Black	5cc0306691	Moved the Bit64 constant out of the regfile.hh into isa_traits.cc, which is the only place it was used. ... --HG-- extra : convert_revision : 0a9bb7134f7a7f981ea40294e0877ce46d7d693e	2006-05-28 23:50:23 -04:00
Gabe Black	981471c31d	Used the Priv and new HPriv instruction formats, which have been tweaked to let some checks be done by the misc reg file. ... --HG-- extra : convert_revision : efee709cbab706bdb8ef7010ce153cd75a0a2ec6	2006-05-28 23:49:29 -04:00
Gabe Black	a433cf140e	Fixed this to run from the newmem directory to be compatible with how things have been moved around. ... --HG-- extra : convert_revision : 378e0976a2ec6188fc0fd3a5bc14101512b6b9e1	2006-05-28 23:48:24 -04:00
Ali Saidi	82a76d18e1	Remove authors from copyright. ... --HG-- extra : convert_revision : 5daba0ab70b4e6d7213bad6aedcb47a0fe56031d	2006-05-28 23:26:15 -04:00
Ali Saidi	de20b819f1	remove some getPtr() calls by changing having function return values ... instead of taking a pointer --HG-- extra : convert_revision : fd9092eaa726e91b501334d35d28dda28aaa01bd	2006-05-28 22:21:57 -04:00
Ali Saidi	5df77b865d	Merge zizzer:/bk/newmem ... into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 3a34dbab3101281786a4b70724c5aee3e4730843	2006-05-26 18:40:08 -04:00
Ali Saidi	e04f60667a	Implement PR/HPR/ASR for full system ... Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. --HG-- extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2	2006-05-26 18:40:00 -04:00
Ali Saidi	f456360bbc	Merge zeep.pool:/z/saidi/work/m5.newmem ... into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 1344e6a30073a1091a904593e6d4733baf19d7e2	2006-05-26 17:03:47 -04:00
Steve Reinhardt	53510f1844	Fixes for TimingSimpleCPU under full system. Now boots Alpha Linux! ... src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: Move traceData->finalize() into postExecute(). src/cpu/simple/timing.cc: Fixes for full system. Now boots Alpha Linux! - Handle ifetch faults, suspend/resume. - Delete memory request & packet objects on response. - Don't try to do split memory accesses on prefetch references (ISA description doesn't support this). src/cpu/simple/timing.hh: Minor reorganization of internal methods. --HG-- extra : convert_revision : 59e3ee5e4cb53c424ebdbe2e504d97e88c08a978	2006-05-26 14:33:43 -04:00
Steve Reinhardt	acb05ebcf6	Reorganize bridge as pair of cooperating ports. ... Store original source & senderState for timing packets that get a response, so we can properly route the response packet back to the original sender. --HG-- extra : convert_revision : 03dbcc8dc06d93de243bfcdc3cbaa012773c6782	2006-05-26 14:29:29 -04:00
Steve Reinhardt	cdad113afb	Add a little more tracing support for Bus/Port stuff. ... src/base/traceflags.py: Sort flags so you can find things. Add BusAddrRanges flag for tracking RangeChange events separately from general bus activity. src/mem/bus.cc: Add BusAddrRanges flag for tracking RangeChange events separately from general bus activity. src/mem/port.cc: src/mem/port.hh: Print Config trace message when peers are set up. --HG-- extra : convert_revision : d7c11d5f90c8de5c8d97e473501a268a567e9e44	2006-05-26 14:24:46 -04:00
Steve Reinhardt	e533fad711	Significant rework of Packet class interface: ... - new constructor guarantees initialization of most fields - flags track status of non-guaranteed fields (addr, size, src) - accessor functions (getAddr() etc.) check status on access - Command & Result classes are nested in Packet class scope - Command now built from vector of behavior bits - string version of Command for tracing - reinitFromRequest() and makeTimingResponse() encapsulate common manipulations of existing packets src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/timing.cc: src/dev/alpha_console.cc: src/dev/ide_ctrl.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/isa_fake.cc: src/dev/ns_gige.cc: src/dev/pciconfigall.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/dev/tsunami_io.cc: src/dev/tsunami_pchip.cc: src/dev/uart8250.cc: src/mem/bus.cc: src/mem/bus.hh: src/mem/physical.cc: src/mem/port.cc: src/mem/port.hh: src/mem/request.hh: Update for new Packet interface. --HG-- extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269	2006-05-26 14:17:33 -04:00
Steve Reinhardt	da6a7b1263	Add names to memory Port objects for tracing. ... --HG-- extra : convert_revision : ddf30084e343e8656e4812ab20356292b35507ee	2006-05-26 13:48:35 -04:00
Kevin Lim	94eff2f485	Merge ktlim@zamp:/z/ktlim2/clean/m5-merge ... into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3 --HG-- extra : convert_revision : d3381ee4907c2b6f1747c4496c980e34913e81e7	2006-05-25 17:56:23 -04:00
Kevin Lim	f1fab2a446	Fix stat typo. ... --HG-- extra : convert_revision : f23d8c50f586fb8f25d4ce992730213f0c301b0f	2006-05-25 17:56:01 -04:00
Kevin Lim	f5b5391cfb	Missed this file in last check in. ... --HG-- extra : convert_revision : 6c42350fc3cebb5cf4a6da8ea0c51cca15b3f99f	2006-05-25 17:13:00 -04:00
Kevin Lim	248bd2bb62	Various branch predictor fixes/cleanup. It works more correctly now and supports both local and tournament predictors. ... cpu/o3/2bit_local_pred.cc: Branch predictor cleanup/fixup. Rename this to LocalBP. cpu/o3/2bit_local_pred.hh: Rename to LocalBP, update to support changes to BPredUnit, include comments. cpu/o3/alpha_cpu_builder.cc: Support extra parameters to the branch predictor. Now it takes in a parameter to tell it which branch predictor it is using, the local or the tournament predictor. cpu/o3/alpha_params.hh: Add in extra parameter for the branch predictor type. cpu/o3/bpred_unit.cc: Branch predictor fixup/cleanup. Rename it to BPredUnit. cpu/o3/bpred_unit.hh: Branch predictor fixup/cleanup. Now supports both the local and tournament predictors, and stores the branch predictor update state. cpu/o3/bpred_unit_impl.hh: Branch predictor overhaul. Now supports both the local and tournament predictors. cpu/o3/cpu_policy.hh: cpu/ozone/ozone_impl.hh: cpu/ozone/simple_impl.hh: Reflect the class name change. cpu/o3/decode_impl.hh: Be sure to set the predicted target as well so we don't squash twice. cpu/o3/tournament_pred.cc: cpu/o3/tournament_pred.hh: Fixes to the tournament predictor. cpu/ozone/simple_params.hh: Include parameter for the branch predictor type. python/m5/objects/AlphaFullCPU.py: python/m5/objects/OzoneCPU.py: Include the parameter for the branch predictor type. --HG-- extra : convert_revision : 34afebb3b40b47accb12558e439ee4cb03df5e64	2006-05-25 17:01:48 -04:00
Kevin Lim	02aa549c9b	Fix minor memory leak. ... --HG-- extra : convert_revision : aa222dd95d833b16b0f474ec156bd6955c2c54c6	2006-05-25 14:41:36 -04:00
Kevin Lim	32509d8387	Fix up kernel stats, allow them to not be used as well. ... arch/alpha/ev5.cc: Fix up some stuff I missed in the last kernel stats checkin. cpu/checker/cpu.cc: Allow the checker to disable its kernel stats. cpu/cpu_exec_context.cc: Allow CPUExecContext to be created without kernelStats. cpu/cpu_exec_context.hh: Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on. --HG-- extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a	2006-05-25 11:50:42 -04:00
Kevin Lim	3fe3523232	Support new flags now used instead of flags in decoder.isa. ... cpu/ozone/front_end_impl.hh: cpu/ozone/lw_back_end_impl.hh: cpu/ozone/lw_lsq_impl.hh: Support new flags added in. --HG-- extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42	2006-05-24 14:31:06 -04:00
Kevin Lim	16df8221ff	Merge ktlim@zizzer:/bk/m5 ... into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3 --HG-- extra : convert_revision : 804302a5edb9d908808861f7f54a4f3cbb22830c	2006-05-23 18:19:04 -04:00
Kevin Lim	5d3a1e8f65	Updates to isa parser to make it see dependencies properly with the new scanner. ... arch/alpha/isa/main.isa: Use automatic path includes thanks to updates to isa parser. arch/isa_parser.py: Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly. --HG-- extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688	2006-05-23 18:18:16 -04:00
Steve Reinhardt	cf826ae296	Minor fixes for full-system timing memory. ... Need to rewrite bus bridge to get any further. src/dev/io_device.cc: Set packet dest on timing responses. src/mem/bus.cc: Fix dest addr bounds check assertion. Add assertion to catch infinite loopbacks. src/mem/physical.cc: Add comment. --HG-- extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896	2006-05-23 17:16:45 -04:00
Kevin Lim	b414c9e736	Merge ktlim@zizzer:/bk/m5 ... into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3 --HG-- extra : convert_revision : 0a6140f3f5e7c454981c5aa2b221224f076e50eb	2006-05-23 17:04:25 -04:00
Kevin Lim	358cf1b117	Rework how instructions are scheduled and executed. ... The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them. Limiting the number of writebacks outstanding must still be done. cpu/o3/iew_impl.hh: Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution). cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: Rework how instructions are scheduled and executed. --HG-- extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55	2006-05-23 17:03:43 -04:00
Kevin Lim	c9ad4a15d6	Cleanup checker. ... cpu/checker/cpu.cc: Cleanup checker, give more useful warning messages. Also fix bug cpu/checker/cpu.hh: Cleanup checker, use forward declaration instead of include. --HG-- extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574	2006-05-23 16:59:13 -04:00
Kevin Lim	6c386396fa	Code cleanup. ... cpu/base_dyn_inst.hh: Code cleanup --HG-- extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7	2006-05-23 16:57:14 -04:00
Kevin Lim	ff3d16ca1f	Move kernel stats out of CPU and into XC. ... arch/alpha/ev5.cc: Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them. --HG-- extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473	2006-05-23 16:51:16 -04:00
Kevin Lim	eeeee7c58f	Add extra flags to help new CPU handle various instructions. ... IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls. arch/alpha/isa/decoder.isa: Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs. cpu/base_dyn_inst.hh: cpu/static_inst.hh: Added extra flags. cpu/o3/iew_impl.hh: cpu/o3/inst_queue_impl.hh: Handle store conditionals specially. cpu/o3/lsq_unit_impl.hh: Extra flags tells if the instruction is a store conditional. cpu/o3/rename_impl.hh: Handle IPR accesses and store conditionals specially. --HG-- extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f	2006-05-23 14:38:16 -04:00
Steve Reinhardt	20051d41d5	Make scons auto-configure stuff per-build-root. ... Undo changes to allow multiple build roots in a single invocation... this would have been too messy to maintain with the auto-configure stuff, and probably isn't useful anyway. --HG-- extra : convert_revision : 32a2d9d7fc980911acc3e7b9430df1ba5a0ee68e	2006-05-22 22:37:56 -04:00
Steve Reinhardt	475a981f6e	Get rid of FastCPU model. ... It doesn't compile, and if we really want this we should start over from scratch and see if we can reuse parts from BaseSimpleCPU (e.g., derive a FastSimpleCPU). SConstruct: src/arch/SConscript: src/cpu/cpu_models.py: Get rid of FastCPU model. --HG-- extra : convert_revision : f3f0362f7292bf21e8e0d4d84c475be8a9789a0c	2006-05-22 22:18:08 -04:00
Steve Reinhardt	3878895264	Fix to SPARC Nop class for multiple CPU models. ... src/arch/sparc/isa/formats/nop.isa: Fix nop header so we can compile with multiple CPU models. (Former code re-defined Nop object for each model.) --HG-- extra : convert_revision : 04e92622edf4dfefd9e149a17f604e17a93707c9	2006-05-22 22:15:22 -04:00
Steve Reinhardt	2af0daa59f	Make CPU_MODELS default to just the two SimpleCPU variants ... for now (since those are the only ones that compile). --HG-- extra : convert_revision : d865afc0626e52bfa3ad1b4817f4530bcacef03e	2006-05-22 22:14:10 -04:00
Steve Reinhardt	a7c95f702c	Clean up libelf handling. ... SConstruct: Clean up libelf handling. Required better handling of per-build-root stuff in general (though libelf is the only thing in that category currently). src/SConscript: No libelf-specific stuff in here anymore. src/base/loader/elf_object.cc: Just need to include gelf.h... it includes libelf.h. --HG-- extra : convert_revision : 3d6bdcf8233bda0ac8d08ff777de323df8aa45ae	2006-05-22 21:51:59 -04:00
Ali Saidi	28ea972942	have multiple global levels (as required by UA2005) ... --HG-- extra : convert_revision : 027b89f3a42a2ba061e892d07aee768ff0afc49d	2006-05-22 17:38:00 -04:00
Kevin Lim	7df1412ccd	Undo changes to instruction flags that has caused statistics to change in regressions. ... This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon. arch/alpha/isa/decoder.isa: Undo changes to instruction flags that has caused statistics to change in regressions. --HG-- extra : convert_revision : c0fa9d55a22cae7c4f02d388870565b205d6fba3	2006-05-22 16:01:25 -04:00
Steve Reinhardt	c88f0810c0	Forgot to delete the now-obsolete mkbuilddir script. ... --HG-- extra : convert_revision : 75bff38425789e30128fa33845fabde8848410fd	2006-05-22 14:41:49 -04:00
Steve Reinhardt	ba2eae5d52	New directory structure: ... - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions. SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure. --HG-- rename : build/SConstruct => SConstruct rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE rename : build/default_options/MIPS_SE => build_opts/MIPS_SE rename : build/default_options/SPARC_SE => build_opts/SPARC_SE rename : Doxyfile => src/Doxyfile rename : SConscript => src/SConscript rename : arch/SConscript => src/arch/SConscript rename : arch/alpha/SConscript => src/arch/alpha/SConscript rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh rename : arch/alpha/process.cc => src/arch/alpha/process.cc rename : arch/alpha/process.hh => src/arch/alpha/process.hh rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/system.hh => src/arch/alpha/system.hh rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh rename : arch/alpha/types.hh => src/arch/alpha/types.hh rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh rename : arch/isa_parser.py => src/arch/isa_parser.py rename : arch/isa_specific.hh => src/arch/isa_specific.hh rename : arch/mips/SConscript => src/arch/mips/SConscript rename : arch/mips/faults.cc => src/arch/mips/faults.cc rename : arch/mips/faults.hh => src/arch/mips/faults.hh rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh rename : arch/mips/process.cc => src/arch/mips/process.cc rename : arch/mips/process.hh => src/arch/mips/process.hh rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh rename : arch/mips/types.hh => src/arch/mips/types.hh rename : arch/mips/utility.hh => src/arch/mips/utility.hh rename : arch/sparc/SConscript => src/arch/sparc/SConscript rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh rename : arch/sparc/process.cc => src/arch/sparc/process.cc rename : arch/sparc/process.hh => src/arch/sparc/process.hh rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh rename : arch/sparc/system.cc => src/arch/sparc/system.cc rename : arch/sparc/system.hh => src/arch/sparc/system.hh rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh rename : base/bitfield.hh => src/base/bitfield.hh rename : base/callback.hh => src/base/callback.hh rename : base/chunk_generator.hh => src/base/chunk_generator.hh rename : base/circlebuf.cc => src/base/circlebuf.cc rename : base/circlebuf.hh => src/base/circlebuf.hh rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh rename : base/cprintf.cc => src/base/cprintf.cc rename : base/cprintf.hh => src/base/cprintf.hh rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh rename : base/crc.cc => src/base/crc.cc rename : base/crc.hh => src/base/crc.hh rename : base/date.cc => src/base/date.cc rename : base/dbl_list.hh => src/base/dbl_list.hh rename : base/endian.hh => src/base/endian.hh rename : base/fast_alloc.cc => src/base/fast_alloc.cc rename : base/fast_alloc.hh => src/base/fast_alloc.hh rename : base/fenv.hh => src/base/fenv.hh rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh rename : base/hashmap.hh => src/base/hashmap.hh rename : base/hostinfo.cc => src/base/hostinfo.cc rename : base/hostinfo.hh => src/base/hostinfo.hh rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh rename : base/inet.cc => src/base/inet.cc rename : base/inet.hh => src/base/inet.hh rename : base/inifile.cc => src/base/inifile.cc rename : base/inifile.hh => src/base/inifile.hh rename : base/intmath.cc => src/base/intmath.cc rename : base/intmath.hh => src/base/intmath.hh rename : base/kgdb.h => src/base/kgdb.h rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h rename : base/loader/object_file.cc => src/base/loader/object_file.cc rename : base/loader/object_file.hh => src/base/loader/object_file.hh rename : base/loader/symtab.cc => src/base/loader/symtab.cc rename : base/loader/symtab.hh => src/base/loader/symtab.hh rename : base/match.cc => src/base/match.cc rename : base/match.hh => src/base/match.hh rename : base/misc.cc => src/base/misc.cc rename : base/misc.hh => src/base/misc.hh rename : base/mod_num.hh => src/base/mod_num.hh rename : base/mysql.cc => src/base/mysql.cc rename : base/mysql.hh => src/base/mysql.hh rename : base/output.cc => src/base/output.cc rename : base/output.hh => src/base/output.hh rename : base/pollevent.cc => src/base/pollevent.cc rename : base/pollevent.hh => src/base/pollevent.hh rename : base/predictor.hh => src/base/predictor.hh rename : base/random.cc => src/base/random.cc rename : base/random.hh => src/base/random.hh rename : base/range.cc => src/base/range.cc rename : base/range.hh => src/base/range.hh rename : base/refcnt.hh => src/base/refcnt.hh rename : base/remote_gdb.cc => src/base/remote_gdb.cc rename : base/remote_gdb.hh => src/base/remote_gdb.hh rename : base/res_list.hh => src/base/res_list.hh rename : base/sat_counter.cc => src/base/sat_counter.cc rename : base/sat_counter.hh => src/base/sat_counter.hh rename : base/sched_list.hh => src/base/sched_list.hh rename : base/socket.cc => src/base/socket.cc rename : base/socket.hh => src/base/socket.hh rename : base/statistics.cc => src/base/statistics.cc rename : base/statistics.hh => src/base/statistics.hh rename : base/stats/events.cc => src/base/stats/events.cc rename : base/stats/events.hh => src/base/stats/events.hh rename : base/stats/flags.hh => src/base/stats/flags.hh rename : base/stats/mysql.cc => src/base/stats/mysql.cc rename : base/stats/mysql.hh => src/base/stats/mysql.hh rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh rename : base/stats/output.hh => src/base/stats/output.hh rename : base/stats/statdb.cc => src/base/stats/statdb.cc rename : base/stats/statdb.hh => src/base/stats/statdb.hh rename : base/stats/text.cc => src/base/stats/text.cc rename : base/stats/text.hh => src/base/stats/text.hh rename : base/stats/types.hh => src/base/stats/types.hh rename : base/stats/visit.cc => src/base/stats/visit.cc rename : base/stats/visit.hh => src/base/stats/visit.hh rename : base/str.cc => src/base/str.cc rename : base/str.hh => src/base/str.hh rename : base/time.cc => src/base/time.cc rename : base/time.hh => src/base/time.hh rename : base/timebuf.hh => src/base/timebuf.hh rename : base/trace.cc => src/base/trace.cc rename : base/trace.hh => src/base/trace.hh rename : base/traceflags.py => src/base/traceflags.py rename : base/userinfo.cc => src/base/userinfo.cc rename : base/userinfo.hh => src/base/userinfo.hh rename : cpu/SConscript => src/cpu/SConscript rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh rename : cpu/cpu_models.py => src/cpu/cpu_models.py rename : cpu/exec_context.hh => src/cpu/exec_context.hh rename : cpu/exetrace.cc => src/cpu/exetrace.cc rename : cpu/exetrace.hh => src/cpu/exetrace.hh rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh rename : cpu/intr_control.cc => src/cpu/intr_control.cc rename : cpu/intr_control.hh => src/cpu/intr_control.hh rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/op_class.cc => src/cpu/op_class.cc rename : cpu/op_class.hh => src/cpu/op_class.hh rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh rename : cpu/pc_event.cc => src/cpu/pc_event.cc rename : cpu/pc_event.hh => src/cpu/pc_event.hh rename : cpu/profile.cc => src/cpu/profile.cc rename : cpu/profile.hh => src/cpu/profile.hh rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh rename : cpu/simple/base.cc => src/cpu/simple/base.cc rename : cpu/simple/base.hh => src/cpu/simple/base.hh rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh rename : cpu/smt.hh => src/cpu/smt.hh rename : cpu/static_inst.cc => src/cpu/static_inst.cc rename : cpu/static_inst.hh => src/cpu/static_inst.hh rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh rename : dev/alpha_access.h => src/dev/alpha_access.h rename : dev/alpha_console.cc => src/dev/alpha_console.cc rename : dev/alpha_console.hh => src/dev/alpha_console.hh rename : dev/baddev.cc => src/dev/baddev.cc rename : dev/baddev.hh => src/dev/baddev.hh rename : dev/disk_image.cc => src/dev/disk_image.cc rename : dev/disk_image.hh => src/dev/disk_image.hh rename : dev/etherbus.cc => src/dev/etherbus.cc rename : dev/etherbus.hh => src/dev/etherbus.hh rename : dev/etherdump.cc => src/dev/etherdump.cc rename : dev/etherdump.hh => src/dev/etherdump.hh rename : dev/etherint.cc => src/dev/etherint.cc rename : dev/etherint.hh => src/dev/etherint.hh rename : dev/etherlink.cc => src/dev/etherlink.cc rename : dev/etherlink.hh => src/dev/etherlink.hh rename : dev/etherpkt.cc => src/dev/etherpkt.cc rename : dev/etherpkt.hh => src/dev/etherpkt.hh rename : dev/ethertap.cc => src/dev/ethertap.cc rename : dev/ethertap.hh => src/dev/ethertap.hh rename : dev/ide_atareg.h => src/dev/ide_atareg.h rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh rename : dev/ide_disk.cc => src/dev/ide_disk.cc rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h rename : dev/io_device.cc => src/dev/io_device.cc rename : dev/io_device.hh => src/dev/io_device.hh rename : dev/isa_fake.cc => src/dev/isa_fake.cc rename : dev/isa_fake.hh => src/dev/isa_fake.hh rename : dev/ns_gige.cc => src/dev/ns_gige.cc rename : dev/ns_gige.hh => src/dev/ns_gige.hh rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh rename : dev/pcidev.cc => src/dev/pcidev.cc rename : dev/pcidev.hh => src/dev/pcidev.hh rename : dev/pcireg.h => src/dev/pcireg.h rename : dev/pitreg.h => src/dev/pitreg.h rename : dev/pktfifo.cc => src/dev/pktfifo.cc rename : dev/pktfifo.hh => src/dev/pktfifo.hh rename : dev/platform.cc => src/dev/platform.cc rename : dev/platform.hh => src/dev/platform.hh rename : dev/rtcreg.h => src/dev/rtcreg.h rename : dev/simconsole.cc => src/dev/simconsole.cc rename : dev/simconsole.hh => src/dev/simconsole.hh rename : dev/simple_disk.cc => src/dev/simple_disk.cc rename : dev/simple_disk.hh => src/dev/simple_disk.hh rename : dev/sinic.cc => src/dev/sinic.cc rename : dev/sinic.hh => src/dev/sinic.hh rename : dev/sinicreg.hh => src/dev/sinicreg.hh rename : dev/tsunami.cc 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sim/stats.hh => src/sim/stats.hh rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh rename : sim/system.cc => src/sim/system.cc rename : sim/system.hh => src/sim/system.hh rename : sim/vptr.hh => src/sim/vptr.hh rename : test/Makefile => src/unittest/Makefile rename : test/bitvectest.cc => src/unittest/bitvectest.cc rename : test/circletest.cc => src/unittest/circletest.cc rename : test/cprintftest.cc => src/unittest/cprintftest.cc rename : test/foo.ini => src/unittest/foo.ini rename : test/genini.py => src/unittest/genini.py rename : test/initest.cc => src/unittest/initest.cc rename : test/initest.ini => src/unittest/initest.ini rename : test/lru_test.cc => src/unittest/lru_test.cc rename : test/nmtest.cc => src/unittest/nmtest.cc rename : test/offtest.cc => src/unittest/offtest.cc rename : test/paramtest.cc => src/unittest/paramtest.cc rename : test/rangetest.cc => src/unittest/rangetest.cc rename : test/sized_test.cc => src/unittest/sized_test.cc rename : test/stattest.cc => src/unittest/stattest.cc rename : test/strnumtest.cc => src/unittest/strnumtest.cc rename : test/symtest.cc => src/unittest/symtest.cc rename : test/tokentest.cc => src/unittest/tokentest.cc rename : test/tracetest.cc => src/unittest/tracetest.cc extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48	2006-05-22 14:29:33 -04:00
Kevin Lim	5a7db55e9a	Threads start off in suspended status now (Korey's changes for SMT). ... --HG-- extra : convert_revision : ad726f9f258e1983d2af5057ff6e5f9d2a5dd072	2006-05-21 01:55:58 -04:00