Gabe Black
|
943b77b9bb
|
ARM: Decode the VLDR instruction.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
4f130683e0
|
ARM: Implement the VLDR instruction.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
dbec303864
|
ARM: Decode all the various forms of vmov.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
ff3996b24d
|
ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
dd1aedc98b
|
ARM: Implement the various versions of VMOV.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
1f059541d6
|
ARM: Add a new RegImmOp base class.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
6976b4890a
|
ARM: Add a RegRegImmOp base class.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
186cfe3ae3
|
ARM: Widen the immediate fields in the misc instruction classes.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
b87ebf382f
|
ARM: Add a function to decode VFP modified immediate constants.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
7eb4d02dd9
|
ARM: Add a function to decode SIMD modified immediate constants.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
abda50173c
|
ARM: Add fp operands to operands.isa.
|
2010-06-02 12:58:12 -05:00 |
|
Gabe Black
|
6365d29c21
|
ARM: Decode the VMRS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
fbf2ad5ae8
|
ARM: Update the set of FP related miscregs.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
aade63a8fe
|
ARM: Implement the VMRS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
a8b56b452c
|
ARM: Decode the VMSR instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
06008c54eb
|
ARM: Implement the VMSR instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
0ff71c7c34
|
ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
c9c4dfc09d
|
ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
c3bf29bbea
|
ARM: Implement the udiv instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
f3e65c2de2
|
ARM: Implement the sdiv instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
5943f0fc84
|
ARM: Ignore writing a bad mode to CPSR with MSR.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
ba33db8fd6
|
ARM: Decode the CPS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
7861b084f6
|
ARM: Implement the CPS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
eb1447302d
|
ARM: Decode the SRS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
bb6fea91da
|
ARM: Implement the SRS instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
dbee6e0c54
|
ARM: Add a base class for SRS.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
239c9af90d
|
ARM: Implement a badMode function that says whether a mode is legal.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
a5ea52bb45
|
ARM: Allow flattening into any mode.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
698ee26c6b
|
ARM: Decode TBB and TBH.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
6fa713a66c
|
ARM: Decode the setend instruction.
|
2010-06-02 12:58:11 -05:00 |
|
Gabe Black
|
4683cd1655
|
ARM: Define the setend instruction.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
fb23297914
|
ARM: Make a base class for instructions that use only an immediate.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
247acd93c4
|
ARM: Decode the arm version of ldrexd.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
3ad31f61c2
|
ARM: Decode the strex instructions.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
54ab07e636
|
ARM: Implement the strex instructions.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
524a8195e1
|
ARM: Set CPSR.E to SCTLR.EE on faults.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
683421e0c6
|
ARM: Warn about not implementing MPU translation, not panic about MMU.
We'll start out with a stbu version of PMSA and switch over to VMSA for the
full implementation.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
6fb5189c47
|
ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
89b1dd5582
|
ARM: Allow access to the RGNR register.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
c3381167c9
|
ARM: Make the MPUIR register report that 1 unified data region is supported.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
3aa8faf177
|
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
faf6c727f6
|
ARM: Respect the E bit of the CPSR when doing loads and stores.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
b6cb6f1874
|
ARM: Zero the micropc when vectoring to a fault.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
1d5233958a
|
ARM: Implement the V7 version of alignment checking.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
7b397925af
|
ARM: Decode the RFE instruction.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
a2cb503ba6
|
ARM: Implement the RFE instruction.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
ec4cd00b11
|
ARM: Add a base class for the RFE instruction.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
1ada9d4880
|
ARM: Make sure some undefined thumb32 instructions fault.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
3caa75d53a
|
ARM: Squash the low order bits of the PC when performing a regular branch.
|
2010-06-02 12:58:10 -05:00 |
|
Gabe Black
|
36eeee0133
|
ARM: When changing the CPSR and branching, make sure the branch is second.
|
2010-06-02 12:58:09 -05:00 |
|