6 commits

Author	SHA1	Message	Date
Nilay Vaish	e979e8d75e	stats: changes due to recent changesets.	2015-01-04 13:02:12 -06:00
Andreas Hansson	df8df4fd0a	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes ... Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.	2014-12-23 09:31:20 -05:00
Andreas Hansson	6489598fb4	stats: Bump stats for fixes, mostly TLB and WriteInvalidate	2014-12-02 06:08:25 -05:00
Andreas Hansson	4583a5114a	stats: Bump regressions to match latest changes ... Updates after timezone hick-up and sorting of dictionary items in the SimObject.	2014-11-12 09:05:25 -05:00
Ali Saidi	2c2c3a4ce9	arm, tests: Forgot the system.terminal files for the new regressions.	2014-10-30 00:04:12 -05:00
Ali Saidi	29cd50e14e	arm, tests: Add 64-bit ARM regression tests	2014-10-29 23:50:15 -05:00