and a physical memory address for DMA
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Changed registers to array and added mapping function to translate between
PCI bus space and physical address space
--HG--
extra : convert_revision : e9dc4de4e7effe8e8e2365298843d6f767b5a289
are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31
dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
--HG--
extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001
dev/tsunami_cchip.cc:
fixed another problem with the interrupt code, should all work now
--HG--
extra : convert_revision : 1d9fe6081b6391e3e09f1c4a9380a30240fac6dc
interrupt to use a different subnumber since both devices could
interrupt at the same time and we don't want to loose one.
dev/tsunami_cchip.cc:
rewrote interrupt code to handle interrupt mask clearing correctly
dev/tsunami_cchip.hh:
changed (post/clear)DRIR to use a interrupt number rather than a vecotr
dev/tsunami_io.cc:
updated for new post/clearDRIR calls
--HG--
extra : convert_revision : 5b39f5e15a66d5eb6e689e6ece62f99b5fa735ab
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
Fix to remote debugger while in PAL code
dev/pcidev.cc:
Remove extra debug printf
--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
Changed base_linux.ini file to use physical addresses
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Fix masking of read/write address to get read/write offset
dev/tsunami_uart.cc:
Fix masking of read/write address to get read/write offset
Also added add_child call that was missed
dev/tsunami_uart.hh:
Changed size to 0x8
--HG--
extra : convert_revision : 1468ca43167bfb28b28c4510401a1ebad683e102
some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
dev/pcidev.cc:
Linux 2.6 writes the latency timer, so it was added to the list of
allowable writes
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
A couple of changes so that the new linux autoconf serial driver thinks
that the serial port exists and configures it
--HG--
extra : convert_revision : 6c026ef754e31de56c9b837ceb8f6be48c8d8d9c
- Make the MemoryController use address ranges (via Range) instead
of an address and a mask
base/remote_gdb.cc:
reflect name change
dev/alpha_access.h:
better include
dev/alpha_console.cc:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- PhysicalMemory::getSize() -> PhysicalMemory::size()
dev/alpha_console.hh:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- get rid of MmapDevice and inherit from FunctionalMemory
--HG--
extra : convert_revision : e3a65c9debf6f899632d62c70781cbdc2826616b
dev/tsunami.cc:
Changed so Tsunami has a pointer to the System to which it belongs.
Now it is derived from generic base class Platform so platform stuff
can be accessed based on the system
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Cleanup and added copyright
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Added event to skip the "calibrate_delay" function, now calculate
loops_per_jiffy based on frequency, interrupt frequency, and constant
sim/system.hh:
Added pointer to generic Platform base class
--HG--
extra : convert_revision : 5bd925eec220a2ca48eb6164d2ecfdec96922c2c
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami.cc:
dev/tsunami.hh:
A bunch of changes to clean up new PCI code and to fix build
--HG--
extra : convert_revision : 71063bcc565c50fc293b323ddce2c8e701f544ff
execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
dev/tsunami.cc:
dev/tsunami.hh:
Change to use AdaptecController with Tsunami
--HG--
extra : convert_revision : 6ff4f9f7ae1959589340b2ab23755b4dbfec4dbc
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
dev/tsunami.hh:
Started commenting code
dev/tsunami_cchip.cc:
removed unneccessary config files
dev/tsunami_io.cc:
Added code to see the value written
dev/tsunami_uart.cc:
conviently one of the addresses the SuperI/O southbridge can be is the same space
as the UART. This stops the simulator from panicing although it should probably be
changed a bit.
--HG--
extra : convert_revision : a3334a2c418ee8228089d0e1791fa78bbb276fe5
special console values separately.
dev/alpha_console.cc:
use new console specific input function
--HG--
extra : convert_revision : 08997d6115d2aac3a26cac2774b3c3fc0cd76ab0
statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
Make most output files use the output directory
base/misc.cc:
send warnings to the outputStream as well
base/trace.cc:
dprintf_stream defaults to cerr
dev/console.cc:
use the output directory for the console output if it exists
dev/etherdump.cc:
dump to the output directory if it exists
sim/builder.cc:
sim/builder.hh:
move constructor and destructor to .cc file
use a function to get the stream that the builder dumps its
output to, and create a separate file in the output directory
if able
sim/main.cc:
statStream -> outputStream
sim/serialize.cc:
dump checkpoints to the output directory if specified
sim/universe.cc:
provide an output stream for simulator output. (This takes place of the
statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
--HG--
extra : convert_revision : 03abce20edbbf7ec19c9ddd8d69ec8485c383532
from cchip register
dev/tsunami_cchip.cc:
added support for figuring out which cpu you are
--HG--
extra : convert_revision : 7862678a259931bb0a5b2ca8ad298a704bd272ec
cpu/exetrace.cc:
added looking for symbols at PC+4 and PC+8 thanks to gcc skiping
setting the gp where it can and jumping <func>+8
dev/console.cc:
commented out weird interrupt per nate's suggestion
dev/tsunami_cchip.cc:
moved rtc flag to correct bit
dev/tsunami_io.cc:
time interrupt will be 1024Hz and at some point be configurable by
linux
dev/tsunami_io.hh:
Timer interrupt will be 1024hz for now and in the future be
configurable by linux
--HG--
extra : convert_revision : 2fcc924c8848eb3c6166d9d517617ed193a2b89a
dev/tsunami_io.cc:
PIC, PIT, RTC implementation for tsunami working so far
dev/tsunami_io.hh:
PIT, PIC, RTC implementation for tlaser working so far
dev/tsunamireg.h:
Added RTC defines
kern/linux/linux_system.cc:
wrote cycle frequency into variable so linux doesn't probe for it.
The support exists, but it takes two seconds of time to do on a real
machine, so forever in the simulator.
--HG--
extra : convert_revision : e0ed7f271ece4ed69c06af35d1b0e8ed848cd138
dev/tsunami_io.cc:
Add RTC event to change the state of a uip bit
dev/tsunami_io.hh:
Add RTC event to change state of an uip bit
--HG--
extra : convert_revision : acde7bdfe152d3e08f7ed53b4c8e910378f6ae67
dev/tsunami_io.cc:
renamed to io instead of dma since it's more than the DMA controller now
dev/tsunami_io.hh:
renamed from dma to io since it's more than dma just now
--HG--
rename : dev/tsunami_dma.cc => dev/tsunami_io.cc
rename : dev/tsunami_dma.hh => dev/tsunami_io.hh
extra : convert_revision : 4ffb69679eb7cea5725fae3446e088899f1f9315
dev/tsunami_dma.cc:
decide actually differentiating between the different i/o requests
would be a better idea
dev/tsunami_dma.hh:
added mask and mode variables, incase they are needed
dev/tsunamireg.h:
added some i/o port defs
--HG--
extra : convert_revision : 5c7a88a8f8c8725359737b399cfa80610149a5f4
