5 commits

Author	SHA1	Message	Date
Korey Sewell	20e9a90edc	updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* ... which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f	2006-03-08 02:05:38 -05:00
Korey Sewell	54b47bc5ae	MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! ... arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37	2006-02-22 03:33:35 -05:00
Korey Sewell	19534176e0	load/store instruction format ... now generates load/store code ... and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a	2006-02-20 14:30:23 -05:00
Korey Sewell	d7ac2b56c2	make MIPS MT instructions decodable ... ... arch/mips/isa/bitfields.isa: extra bitfield for decoding --HG-- extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866	2006-02-14 02:03:14 -05:00
Korey Sewell	d30262d480	name changes ... minor IntOP format change ... arch/mips/isa/formats/int.format: Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from their reg-reg counterparts --HG-- rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc	2006-02-07 18:36:08 -05:00

Renamed from arch/mips/isa/bitfields.def (Browse further)