sanchayanmaity/gem5 - Sanchayan Maity's repositories

sanchayanmaity/gem5

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Author	SHA1	Message	Date
Brad Beckmann	90d6e2652f	ruby: included ruby config parameter ports per core Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.	2009-11-18 13:55:58 -08:00
Brad Beckmann	3cf24f9716	ruby: Support for merging ALPHA_FS and ruby Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.	2009-11-18 13:55:58 -08:00
Nathan Binkert	da704f52e5	ruby: Fix RubyMemory to work with the newer ruby.	2009-07-06 15:49:47 -07:00

Author

SHA1

Message

Date

Brad Beckmann

90d6e2652f

ruby: included ruby config parameter ports per core

Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.

2009-11-18 13:55:58 -08:00

Brad Beckmann

3cf24f9716

ruby: Support for merging ALPHA_FS and ruby

Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.

2009-11-18 13:55:58 -08:00

Nathan Binkert

da704f52e5

ruby: Fix RubyMemory to work with the newer ruby.

2009-07-06 15:49:47 -07:00

3 commits