Commit graph

9 commits

Author SHA1 Message Date
Gabe Black
4950798268 X86: Implement tlb invalidation and make it happen some of the times it should.
--HG--
extra : convert_revision : 376516d33cd539fa526c834ef2b2c33069af3040
2007-11-12 14:39:07 -08:00
Gabe Black
f1f5dd79bf X86: Implement the wrcr microop which writes a control register, and some control register work.
--HG--
extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab
2007-11-12 14:38:59 -08:00
Gabe Black
d89d80a5d0 X86: Make some of the bits of CR0 do what they're supposed to.
--HG--
extra : convert_revision : 13e79ef1ef09bd842d5e075e31f98ab2a4357901
2007-11-12 14:38:02 -08:00
Gabe Black
e410a925df X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
2007-08-04 20:12:54 -07:00
Gabe Black
387f00e3dd Fill out the miscreg file and add types to miscregs.hh
--HG--
extra : convert_revision : 865432256518c4340d9f319bdd9b7d160dc656a0
2007-07-18 16:12:39 -07:00
Ali Saidi
49527ab553 Merge zizzer:/bk/newmem
into  zeep.pool:/tmp/newmem

--HG--
extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
2007-03-07 15:04:44 -05:00
Ali Saidi
689cab36c9 *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-07 15:04:31 -05:00
Gabe Black
05c86ec0d7 Get X86 to load an elf and start a process for it.
src/arch/x86/SConscript:
    Add in process source files.
src/arch/x86/isa_traits.hh:
    Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
    Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
    An X86 process class.
src/base/loader/elf_object.cc:
    Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
    Add an x86 traceflag
src/sim/process.cc:
    Add in code to create an x86 process.
src/arch/x86/intregs.hh:
    A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
    A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
    An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
    The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
    The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
    An x86 hello world test binary.

--HG--
extra : convert_revision : f22919e010c07aeaf5757dca054d9877a537fd08
2007-03-06 15:42:30 +00:00
Gabe Black
a46e100bd9 Add some new source files.
--HG--
extra : convert_revision : 94f3f19eb91b7f54918640b7605008eb1fe75fc7
2007-03-05 17:56:26 +00:00