Fill out the miscreg file and add types to miscregs.hh
--HG-- extra : convert_revision : 865432256518c4340d9f319bdd9b7d160dc656a0
This commit is contained in:
Gabe Black
parent
5cca5ca3d9
commit
387f00e3dd
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@ -86,6 +86,7 @@
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*/
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#include "arch/x86/miscregfile.hh"
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#include "sim/serialize.hh"
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using namespace X86ISA;
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using namespace std;
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@ -105,31 +106,65 @@ void MiscRegFile::clear()
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MiscReg MiscRegFile::readRegNoEffect(int miscReg)
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{
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panic("No misc registers in x86 yet!\n");
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switch(miscReg)
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{
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case MISCREG_CR1:
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case MISCREG_CR5:
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case MISCREG_CR6:
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case MISCREG_CR7:
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case MISCREG_CR9:
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case MISCREG_CR10:
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case MISCREG_CR11:
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case MISCREG_CR12:
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case MISCREG_CR13:
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case MISCREG_CR14:
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case MISCREG_CR15:
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panic("Tried to read invalid control register %d\n", miscReg);
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break;
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}
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return regVal[miscReg];
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}
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MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
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{
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panic("No misc registers in x86 yet!\n");
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warn("No miscreg effects implemented yet!\n");
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return readRegNoEffect(miscReg);
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}
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void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
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{
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panic("No misc registers in x86 yet!\n");
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switch(miscReg)
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{
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case MISCREG_CR1:
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case MISCREG_CR5:
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case MISCREG_CR6:
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case MISCREG_CR7:
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case MISCREG_CR9:
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case MISCREG_CR10:
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case MISCREG_CR11:
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case MISCREG_CR12:
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case MISCREG_CR13:
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case MISCREG_CR14:
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case MISCREG_CR15:
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panic("Tried to write invalid control register %d\n", miscReg);
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break;
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}
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regVal[miscReg] = val;
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}
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void MiscRegFile::setReg(int miscReg,
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const MiscReg &val, ThreadContext * tc)
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{
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panic("No misc registers in x86 yet!\n");
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warn("No miscreg effects implemented yet!\n");
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setRegNoEffect(miscReg, val);
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}
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void MiscRegFile::serialize(std::ostream & os)
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{
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panic("No misc registers in x86 yet!\n");
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SERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
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{
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panic("No misc registers in x86 yet!\n");
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UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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@ -89,6 +89,7 @@
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#define __ARCH_X86_MISCREGFILE_HH__
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#include "arch/x86/faults.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/types.hh"
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#include <string>
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@ -100,11 +101,14 @@ namespace X86ISA
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std::string getMiscRegName(RegIndex);
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//These will have to be updated in the future.
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const int NumMiscArchRegs = 0;
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const int NumMiscRegs = 0;
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const int NumMiscArchRegs = NUM_MISCREGS;
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const int NumMiscRegs = NUM_MISCREGS;
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class MiscRegFile
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{
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protected:
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MiscReg regVal[NumMiscRegs];
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public:
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void clear();
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@ -73,6 +73,101 @@ namespace X86ISA
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OFBit = 1 << 11
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};
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enum MiscRegIndex
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{
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// Control registers
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// Most of these are invalid.
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MISCREG_CR0,
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MISCREG_CR1,
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MISCREG_CR2,
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MISCREG_CR3,
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MISCREG_CR4,
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MISCREG_CR5,
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MISCREG_CR6,
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MISCREG_CR7,
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MISCREG_CR8,
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MISCREG_CR9,
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MISCREG_CR10,
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MISCREG_CR11,
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MISCREG_CR12,
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MISCREG_CR13,
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MISCREG_CR14,
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MISCREG_CR15,
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// Debug registers
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MISCREG_DR0,
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MISCREG_DR1,
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MISCREG_DR2,
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MISCREG_DR3,
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MISCREG_DR4,
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MISCREG_DR5,
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MISCREG_DR6,
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MISCREG_DR7,
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// Flags register
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MISCREG_RFLAGS,
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// Segment selectors
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MISCREG_ES,
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MISCREG_CS,
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MISCREG_SS,
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MISCREG_DS,
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MISCREG_FS,
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MISCREG_GS,
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// Hidden segment base field
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MISCREG_ES_BASE,
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MISCREG_CS_BASE,
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MISCREG_SS_BASE,
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MISCREG_DS_BASE,
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MISCREG_FS_BASE,
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MISCREG_GS_BASE,
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// Hidden segment limit field
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MISCREG_ES_LIMIT,
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MISCREG_CS_LIMIT,
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MISCREG_SS_LIMIT,
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MISCREG_DS_LIMIT,
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MISCREG_FS_LIMIT,
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MISCREG_GS_LIMIT,
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// Hidden segment limit attributes
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MISCREG_ES_ATTR,
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MISCREG_CS_ATTR,
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MISCREG_SS_ATTR,
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MISCREG_DS_ATTR,
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MISCREG_FS_ATTR,
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MISCREG_GS_ATTR,
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// System segment selectors
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MISCREG_LDTR,
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MISCREG_TR,
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// Hidden system segment base field
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MISCREG_LDTR_BASE,
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MISCREG_TR_BASE,
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MISCREG_GDTR_BASE,
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MISCREG_IDTR_BASE,
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// Hidden system segment limit field
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MISCREG_LDTR_LIMIT,
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MISCREG_TR_LIMIT,
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MISCREG_GDTR_LIMIT,
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MISCREG_IDTR_LIMIT,
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// Hidden system segment attribute field
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MISCREG_LDTR_ATTR,
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MISCREG_TR_ATTR,
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//XXX Add "Model-Specific Registers"
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NUM_MISCREGS
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};
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/**
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* A type to describe the condition code bits of the RFLAGS register,
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* plus two flags, EZF and ECF, which are only visible to microcode.
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*/
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BitUnion64(CCFlagBits)
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Bitfield<11> OF;
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Bitfield<7> SF;
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@ -83,6 +178,152 @@ namespace X86ISA
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Bitfield<2> PF;
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Bitfield<0> CF;
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EndBitUnion(CCFlagBits)
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/**
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* RFLAGS
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*/
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BitUnion64(RFLAGS)
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Bitfield<21> ID; // ID Flag
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Bitfield<20> VIP; // Virtual Interrupt Pending
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Bitfield<19> VIF; // Virtual Interrupt Flag
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Bitfield<18> AC; // Alignment Check
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Bitfield<17> VM; // Virtual-8086 Mode
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Bitfield<16> RF; // Resume Flag
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Bitfield<14> NT; // Nested Task
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Bitfield<13, 12> IOPL; // I/O Privilege Level
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Bitfield<11> OF; // Overflow Flag
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Bitfield<10> DF; // Direction Flag
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Bitfield<9> IF; // Interrupt Flag
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Bitfield<8> TF; // Trap Flag
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Bitfield<7> SF; // Sign Flag
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Bitfield<6> ZF; // Zero Flag
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Bitfield<4> AF; // Auxiliary Flag
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Bitfield<2> PF; // Parity Flag
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Bitfield<0> CF; // Carry Flag
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EndBitUnion(RFLAGS)
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/**
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* Control registers
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*/
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BitUnion64(CR0)
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Bitfield<31> PG; // Paging
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Bitfield<30> CD; // Cache Disable
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Bitfield<29> NW; // Not Writethrough
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Bitfield<18> AM; // Alignment Mask
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Bitfield<16> WP; // Write Protect
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Bitfield<5> NE; // Numeric Error
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Bitfield<4> ET; // Extension Type
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Bitfield<3> TS; // Task Switched
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Bitfield<2> EM; // Emulation
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Bitfield<1> MP; // Monitor Coprocessor
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Bitfield<0> PE; // Protection Enabled
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EndBitUnion(CR0)
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// Page Fault Virtual Address
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BitUnion64(CR2)
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Bitfield<31, 0> legacy;
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EndBitUnion(CR2)
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BitUnion64(CR3)
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Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
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// Base Address
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Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
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// Base Address
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Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
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// Base Address
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Bitfield<4> PCD; // Page-Level Cache Disable
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Bitfield<3> PWT; // Page-Level Writethrough
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EndBitUnion(CR3)
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BitUnion64(CR4)
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Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
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// Exception Support
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Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
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Bitfield<8> PCE; // Performance-Monitoring Counter Enable
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Bitfield<7> PGE; // Page-Global Enable
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Bitfield<6> MCE; // Machine Check Enable
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Bitfield<5> PAE; // Physical-Address Extension
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Bitfield<4> PSE; // Page Size Extensions
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Bitfield<3> DE; // Debugging Extensions
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Bitfield<2> TSD; // Time Stamp Disable
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Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
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Bitfield<0> VME; // Virtual-8086 Mode Extensions
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EndBitUnion(CR4)
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BitUnion64(CR8)
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Bitfield<3, 0> TPR; // Task Priority Register
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EndBitUnion(CR4)
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/**
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* Segment Selector
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*/
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BitUnion64(SegSelector)
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Bitfield<15, 3> SI; // Selector Index
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Bitfield<2> TI; // Table Indicator
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Bitfield<1, 0> RPL; // Requestor Privilege Level
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EndBitUnion(SegSelector)
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/**
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* Segment Descriptors
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*/
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BitUnion64(SegDescriptor)
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Bitfield<63, 56> baseHigh;
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Bitfield<39, 16> baseLow;
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Bitfield<55> G; // Granularity
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Bitfield<54> D; // Default Operand Size
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Bitfield<54> B; // Default Operand Size
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Bitfield<53> L; // Long Attribute Bit
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Bitfield<52> AVL; // Available To Software
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Bitfield<51, 48> limitHigh;
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Bitfield<15, 0> limitLow;
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Bitfield<47> P; // Present
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Bitfield<46, 45> DPL; // Descriptor Privilege-Level
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Bitfield<44> S; // System
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SubBitUnion(type, 43, 40)
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// Specifies whether this descriptor is for code or data.
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Bitfield<43> codeOrData;
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// These bit fields are for code segments
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Bitfield<42> C; // Conforming
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Bitfield<41> R; // Readable
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// These bit fields are for data segments
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Bitfield<42> E; // Expand-Down
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Bitfield<41> W; // Writable
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// This is used for both code and data segments.
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Bitfield<40> A; // Accessed
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EndSubBitUnion(type)
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EndBitUnion(SegDescriptor)
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BitUnion64(GateDescriptor)
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Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
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Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
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Bitfield<31, 16> selector; // Target Code-Segment Selector
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Bitfield<47> P; // Present
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Bitfield<46, 45> DPL; // Descriptor Privilege-Level
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Bitfield<43, 40> type;
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Bitfield<36, 32> count; // Parameter Count
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EndBitUnion(GateDescriptor)
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/**
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* Descriptor-Table Registers
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*/
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BitUnion64(GDTR)
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EndBitUnion(GDTR)
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BitUnion64(IDTR)
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EndBitUnion(IDTR)
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BitUnion64(LDTR)
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EndBitUnion(LDTR)
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/**
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* Task Register
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*/
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BitUnion64(TR)
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EndBitUnion(TR)
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};
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#endif // __ARCH_X86_INTREGS_HH__
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