sanchayanmaity/gem5
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9 commits

Author SHA1 Message Date
Korey Sewell
b3464ef180 support for unaligned memory access 
arch/mips/isa/base.isa:
    disassembly fixes
arch/mips/isa/decoder.isa:
    support for unaligned loads/stores
arch/mips/isa_traits.hh:
    edit Syscall Reg values
arch/mips/linux_process.cc:
    call writevFunc on writev syscall

--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
 2006-03-19 13:40:03 -05:00
Korey Sewell
805b9cf1d5 Found and fixed 3 decoder.isa bugs!!! Now the hello_world program runs for a while 
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet

arch/mips/faults.cc:
    more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
    make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
    FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
    FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
    FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
    change back to original way
base/loader/elf_object.hh:
    change back to original!

--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
 2006-03-16 18:39:54 -05:00
Korey Sewell
20e9a90edc updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* 
which I need to update the misc. regfile accesses

arch/mips/faults.cc:
arch/mips/faults.hh:
    alpha to mips
arch/mips/isa/base.isa:
    add includes
arch/mips/isa/bitfields.isa:
    more bitfields
arch/mips/isa/decoder.isa:
    lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
    include cop0.isa
arch/mips/isa/formats/basic.isa:
    fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
    merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
    merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
    need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
    file copied over

--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
 2006-03-08 02:05:38 -05:00
Korey Sewell
54b47bc5ae MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! 
arch/mips/faults.hh:
    remove nonsense
arch/mips/isa/base.isa:
    define R31
arch/mips/isa/bitfields.isa:
    forgotten bitfields
arch/mips/isa/decoder.isa:
    INT64 -> int64_t
arch/mips/isa/formats.isa:
    fix comments
arch/mips/isa/formats/branch.isa:
    Branch -> BranchLikely
    RB -> RT
arch/mips/isa/formats/fp.isa:
    Make FP ops generates
arch/mips/isa/formats/mem.isa:
    RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
    Rc -> Rd
arch/mips/isa/formats/util.isa:
    forgot brace and semicolon
arch/mips/isa/includes.isa:
    remove unnecessary files
arch/mips/isa_traits.hh:
    spacing
cpu/static_inst.hh:
    add cond_delay_slot flag

--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
 2006-02-22 03:33:35 -05:00
Korey Sewell
a4799a89de Renaming alpha files and changing some MIPS stuff to be more like Alpha version 
SConscript:
    changed the alpha_memory.hh to memory.hh in SConscript
arch/isa_parser.py:
    temporarily comment out o3 model
arch/mips/isa/base.isa:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    Fix Up Base Class to mirror how Alpha generates StaticInsts
arch/mips/faults.cc:
    MIPS fault.cc file
arch/mips/faults.hh:
    MIPS fault.hh file

--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
 2006-02-21 22:02:05 -05:00
Korey Sewell
bdf3fd92ba make MIPS specific 
--HG--
extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
 2006-02-20 14:48:10 -05:00
Korey Sewell
a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly 
Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
 2006-02-18 23:17:45 -05:00
Korey Sewell
7c9ea671af file name changes ... minor ISA changes 
arch/mips/isa/base.isa:
    restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
    add c++ emacs header
arch/mips/isa/formats/branch.isa:
    added branch likely format
arch/mips/isa/formats/int.isa:
    small change to python code

--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
 2006-02-16 02:39:46 -05:00
Korey Sewell
a0cdf213ab ... 
arch/mips/isa/base.isa:
    restore base.isa

--HG--
extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
 2006-02-15 14:08:54 -05:00