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sanchayanmaity/gem5

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Author	SHA1	Message	Date
Gabe Black	00f24ae92c	Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.	2011-02-03 20:23:00 -08:00
Gabe Black	119f5f8e94	X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.	2011-02-01 18:28:41 -08:00
Lisa Hsu	a70f70ccbf	configs: pull out cache configuration code from se.py and fs.py. Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.	2010-02-25 10:13:40 -08:00

Author

SHA1

Message

Date

Gabe Black

00f24ae92c

Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

2011-02-03 20:23:00 -08:00

Gabe Black

119f5f8e94

X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.

2011-02-01 18:28:41 -08:00

Lisa Hsu

a70f70ccbf

configs: pull out cache configuration code from se.py and fs.py.

Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.

2010-02-25 10:13:40 -08:00

3 commits