Commit graph

10 commits

Author SHA1 Message Date
Gabe Black
cdc585e0e8 SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
Ali Saidi
1158da37fb Panic if any CMT registers are accessed
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add CMT ASI registers
src/arch/sparc/tlb.cc:
    Panic if any of the CMT registers are being accessed

--HG--
extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
2007-03-08 21:49:13 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Ali Saidi
5f662d451e clean up fault code a little bit
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it

src/arch/sparc/asi.cc:
    make AsiIsLittle() be all the little asis.
    Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
    clean up the do*Fault code.... Make it work like legion, in particular
    pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
    implement some more twin ASIs
src/arch/sparc/tlb.cc:
    All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
    softint is supported now, no more need to

--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
2007-01-22 21:55:43 -05:00
Ali Saidi
fa4293af33 flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff

src/arch/sparc/asi.cc:
    flesh out twinx asis
src/arch/sparc/miscregfile.cc:
    fix TICK register reads
src/arch/sparc/tlb.cc:
    reduce the number of readmiscreg accesses,
    implement tsb pointer stuff

--HG--
extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-14 19:01:21 -05:00
Ali Saidi
ed22eb781d get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07 18:50:33 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
Ali Saidi
271b9a5435 first cut at a sparc tlb
src/arch/sparc/SConscript:
    Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    update asi names for how they're listed in the supplement
    add asis
    add more asi functions
src/arch/sparc/isa_traits.hh:
    move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add mmu registers to tlb
    get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
    make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    first cut at sparc tlb
src/arch/sparc/vtophys.hh:
    pagatable nedes to be included here
src/mem/request.hh:
    add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
    fix incorrect definition of LL

--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
2006-11-23 01:42:57 -05:00
Gabe Black
333eb4efea Basic work towards supporting ASIs properly
src/arch/sparc/SConscript:
    Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface.
src/arch/sparc/asi.hh:
    Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions.
src/arch/sparc/asi.cc:
    Implementation of some ASI utility functions.

--HG--
extra : convert_revision : 8021007027b13e91cc66908029470da49a8ca11f
2006-09-30 03:03:58 -04:00