Commit graph

7964 commits

Author SHA1 Message Date
Steve Reinhardt
89cf3f6e85 Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.

--HG--
rename : src/base/sched_list.hh => src/cpu/sched_list.hh
rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2011-01-03 14:35:47 -08:00
Steve Reinhardt
2f4c71968a Delete unused files from src/base directory. 2011-01-03 14:35:45 -08:00
Steve Reinhardt
c69d48f007 Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
2011-01-03 14:35:43 -08:00
Gabe Black
1a10ccc5e5 RefCount: Fix reference counting pointer == and != with a T* on the left.
These operators were expecting a const T& instead of a const T*, and were not
being picked up and used by gcc in the right places as a result. Apparently no
one used these operators before. A unit test which exposed these problems,
verified the solution, and checks other basic functionality is on the way.
2011-01-03 15:31:20 -05:00
Nilay Vaish
5e25f31712 Ruby: Add option for random seed to Ruby.py
This patch adds an option to the script Ruby.py for setting the parameter
m_random_seed used for randomizing delays in the memory system. The option
can be specified as "--random_seed <seed value>".
2011-01-03 12:40:31 -06:00
Nathan Binkert
d6ad7419ff swig: use <> for system %includes instead of "" 2010-12-30 12:51:04 -05:00
Nathan Binkert
fe6574ecc0 style: make style hook work with pre-qrefresh and update to use new code
clean up the code a little bit while we're at it.

I recommend that everyone adds the pre-qrefresh hook below since it
will make qref run the style hook and not just commit/qpush

[extensions]
style = <m5 path>/util/style.py

[hooks]
pretxncommit.style = python:style.check_whitespace
pre-qrefresh.style = python:style.check_whitespace
2010-12-30 12:53:56 -05:00
Nilay Vaish
04f5bb34ce PerfectCacheMemory: Add return statements to two functions.
Two functions in src/mem/ruby/system/PerfectCacheMemory.hh, tryCacheAccess()
and cacheProbe(), end with calls to panic(). Both of these functions have
return type other than void. Any file that includes this header file fails
to compile because of the missing return statement. This patch adds dummy
values so as to avoid the compiler warnings.
2010-12-23 13:36:18 -06:00
Nilay Vaish
58fa2857e1 This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh 2010-12-22 23:15:24 -06:00
Steve Reinhardt
2c0e80f96b memtest: delete some crufty dead code 2010-12-21 22:57:29 -08:00
Steve Reinhardt
3e0ed66ff2 Get rid of unused file src/base/dbl_list.hh 2010-12-21 22:39:26 -08:00
Nathan Binkert
88033eb608 stats: allow stats to be reset even if no objects have been instantiated 2010-12-21 08:02:41 -08:00
Nathan Binkert
c24f1df343 importer: fix error message 2010-12-21 08:02:40 -08:00
Nathan Binkert
a7d9e5c9e0 scons: remove extra dependencies 2010-12-21 08:02:39 -08:00
Gabe Black
672d6a4b98 Style: Replace some tabs with spaces. 2010-12-20 16:24:40 -05:00
Gabe Black
89850d6370 Params: Fix a broken error message in verifyIp. 2010-12-20 04:20:58 -05:00
Gabe Black
2ff3e6b399 ARM: Take advantage of new PCState syntax. 2010-12-09 14:45:17 -08:00
Gabe Black
24c5b5925d ARM: Get rid of some unused FP operands. 2010-12-09 14:45:04 -08:00
Gabe Black
55978f0395 Merge. 2010-12-08 16:52:38 -08:00
Brad Beckmann
7e42b753e7 ruby: remove Ruby asserts for m5.fast
This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.
2010-12-08 11:52:02 -08:00
Gabe Black
5a895ab92c Alpha: Take advantage of new PCState syntax. 2010-12-08 10:55:33 -08:00
Gabe Black
f26051eb1a MIPS: Take advantage of new PCState syntax. 2010-12-08 10:45:14 -08:00
Gabe Black
7f3f90f71d POWER: Take advantage of new PCState syntax. 2010-12-08 10:33:03 -08:00
Gabe Black
f01d2efe8a SPARC: Take advantage of new PCState syntax. 2010-12-08 00:27:43 -08:00
Gabe Black
d3e021820e X86: Take advantage of new PCState syntax. 2010-12-08 00:27:23 -08:00
Gabe Black
4c9b023a7a ISA: Get the parser to support pc state components more elegantly. 2010-12-07 23:08:05 -08:00
Ali Saidi
18555c1b56 Configs: Automatically choose the correct hello world binary. 2010-12-07 16:19:57 -08:00
Ali Saidi
42ba158479 O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
2010-12-07 16:19:57 -08:00
Ali Saidi
1cfe2c8820 Stats: Fix stats for cumulative flags change. 2010-12-07 16:19:57 -08:00
Ali Saidi
e681c0f7b3 O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
2010-12-07 16:19:57 -08:00
Giacomo Gabrielli
719f9a6d4f O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR.  Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes.  Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-07 16:19:57 -08:00
Min Kyu Jeong
4bbdd6ceb2 O3: Support SWAP and predicated loads/store in ARM. 2010-12-07 16:19:57 -08:00
Ali Saidi
21bfbd422c ARM: Support switchover with hardware table walkers 2010-12-07 16:19:57 -08:00
Nilay Vaish
658849d101 ruby: Converted old ruby debug calls to M5 debug calls
This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
2010-12-01 11:30:04 -08:00
Ali Saidi
0f039fe447 IGbE: return 0 on an invalid descriptor size instead of -1.
Asserts where descSize() get called with assert if we end up returning
0.
2010-11-26 20:47:23 -05:00
Gabe Black
7f6ca0981f Copyright: Add AMD copyright to the param changes I just made. 2010-11-23 17:08:41 -05:00
Gabe Black
b3de4855c3 Params: Add parameter types for IP addresses in various forms.
New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
2010-11-23 15:54:43 -05:00
Gabe Black
40d434d551 X86: Loosen an assert for x86 and connect the APIC ports when caches are used. 2010-11-23 06:11:50 -05:00
Gabe Black
3cd349f443 X86: Obey the PCD (cache disable) bit in the page tables. 2010-11-23 06:10:17 -05:00
Gabe Black
c8c921b9db X86: Mark IO space accesses as uncachable. 2010-11-22 05:49:03 -05:00
Gabe Black
cb3674cd27 X86: Remove reserved* from the m5 utility program for x86. 2010-11-22 05:47:54 -05:00
Gabe Black
6a00519e73 IDE,X86: Fix IDE controller BAR configuration for x86. 2010-11-22 02:33:47 -05:00
Nathan Binkert
4d9ff1954b random: small comment about our random number generator and its origin 2010-11-20 12:12:27 -08:00
Ali Saidi
34a8e37c13 SE: Fix simulating more than 4GB of RAM in SE mode
This change removes some dead code in PhysicalMemory, uses a 64 bit type
for the page pointer in System (instead of 32 bit) and cleans up some style.
2010-11-19 18:01:01 -06:00
Ali Saidi
5c6f4a0f17 SCons: Fix compilation on OS X 2010-11-19 18:00:59 -06:00
Ali Saidi
e1b9a815dd SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
Gabe Black
92655b6399 O3: Fix fp destination register flattening, and index offset adjusting.
This change makes O3 flatten floating point destination registers, and also
fixes misc register flattening so that it's correctly repositioned relative to
the resized regions for integer and floating point indices.

It also fixes some overly long lines.
2010-11-18 13:11:36 -05:00
Gabe Black
4876e0c92b Config: Change misleading "cycle" message to say "tick".
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
2010-11-17 23:16:19 -05:00
Gabe Black
0e41d4e5ea Stats: Update the O3 fetch stats for SPARC. 2010-11-15 19:37:15 -08:00
Gabe Black
8b9b85e92c O3: Make O3 support variably lengthed instructions. 2010-11-15 19:37:03 -08:00