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Author SHA1 Message Date
Nathan Binkert
934523c3a0 rename AlphaConsole to AlphaBackdoor 
--HG--
rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py
rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc
rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
 2008-06-17 20:36:39 -07:00
Nathan Binkert
6ff4539901 Change the default output filename for the terminal so it's more obvious. 
--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
 2008-06-17 20:30:37 -07:00
Nathan Binkert
00df9016fe Rename SimConsole to Terminal since it makes more sense 
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
 2008-06-17 20:29:06 -07:00
Nathan Binkert
fa8f91fdc0 physmem: Add a null option to physical memory so it doesn't store data. 2008-06-15 21:39:29 -07:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Nathan Binkert
b429b1759d params: Prevent people from setting attributes on vector params. 2008-06-15 21:26:33 -07:00
Nathan Binkert
6dedc645f7 add compile flags to m5 2008-06-15 20:56:35 -07:00
Nathan Binkert
b2036bfda8 Command line option to print out List of SimObjects and their parameters 2008-06-14 21:51:08 -07:00
Nathan Binkert
bbeb8082a5 main: add .m5/options.py processing. This file is processed before 
arguments are parsed so that they can change the default options for
various config parameters.
 2008-06-14 21:16:00 -07:00
Nathan Binkert
fc48d1dcf5 Add .m5 configuration directory 2008-06-14 21:15:59 -07:00
Nathan Binkert
779c31077c python: Separate the options parsing stuff. Remove options parsing stuff from 
main.py so things are a bit more obvious.
 2008-06-14 21:15:58 -07:00
Nathan Binkert
4afdc40d70 params: Fix the memory bandwidth parameter 2008-06-14 20:42:45 -07:00
Nathan Binkert
3d2e7797cc params: Fix floating point parameters 2008-06-14 20:39:31 -07:00
Nathan Binkert
f82d4e2364 python: Move various utility classes into a new m5.util package so 
they're all in the same place.  This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication.  Lots of improvements to the utility as well.

--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
 2008-06-14 20:19:49 -07:00
Nathan Binkert
fe325c7f43 MemReq: Add option to reset the time on a request. 2008-06-14 19:39:01 -07:00
Nathan Binkert
ed84388b85 Add hg commands for style check so you can check at times other than commit 2008-06-14 19:37:26 -07:00
Nathan Binkert
ce43e46576 Fix various SWIG warnings 2008-06-14 12:57:21 -07:00
Nathan Binkert
7a58b5a38a Add missing dependencies on .i files 2008-06-14 12:10:50 -07:00
Nathan Binkert
2d037682ff scons: proper fix for hg version stuff 2008-06-14 10:30:18 -07:00
Nathan Binkert
fe4fd9f414 scons: fix program_info.cc generation 2008-06-13 17:34:22 -07:00
Steve Reinhardt
dace77dc4a Automated merge with ssh://m5sim.org//repo/m5 2008-06-13 01:59:10 -04:00
Steve Reinhardt
caccbd1edc Get rid of bogus bus assertion. 
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
 2008-06-13 01:33:49 -04:00
Steve Reinhardt
024ec4c5c3 Get rid of bogus cache assertion. 
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
 2008-06-13 01:29:20 -04:00
Ali Saidi
7e6728450f Scripts: Check for the appropriate build type as soon as possible. 2008-06-13 01:09:06 -04:00
Ali Saidi
907b28cc62 HG: Add compiled hg revision and date to the standard M5 output. 2008-06-13 01:09:04 -04:00
Gabe Black
2b4874449c Alpha: Get rid of an old include of a non-existant file. 2008-06-12 01:54:21 -04:00
Gabe Black
7be8e671f1 Params: Allow nested namespaces in cxx_namespace 2008-06-12 01:00:29 -04:00
Gabe Black
5b5875341c X86: Make the cpuid processor identifier return a real string. 2008-06-12 01:00:19 -04:00
Gabe Black
c625cf0ae1 X86: Make the code compile as 32 bit. 2008-06-12 01:00:05 -04:00
Gabe Black
23c04b8c66 Params: Remove an unnecessary include. 2008-06-12 00:59:58 -04:00
Gabe Black
bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black
4f4ff17578 X86: Make the disassembly for halt conform with the other microops. 2008-06-12 00:58:27 -04:00
Gabe Black
31d40ad7c2 X86: Implement and hook up STI and CLI instructions. 2008-06-12 00:58:19 -04:00
Gabe Black
da20c0ec54 X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports. 2008-06-12 00:58:13 -04:00
Gabe Black
1f5b992b58 X86: Make the platform object initialize channel 0 of the PIT. 2008-06-12 00:56:54 -04:00
Gabe Black
16e26fbf03 X86: Hook the speaker device to the pit device. 2008-06-12 00:56:17 -04:00
Gabe Black
da7f512067 Timer: Fill out the periodic modes a little. 2008-06-12 00:56:07 -04:00
Gabe Black
4f9a0402f6 Dev: Seperate the 8254 timer from tsunami and use it in that and the PC. 2008-06-12 00:54:48 -04:00
Gabe Black
0368ccdeda BitUnion: Take out namespace declaration so bitunions can be declared inside classes. 2008-06-12 00:54:32 -04:00
Gabe Black
81936ae2ed X86: Add an event for the apic timer timeout. It doesn't get used yet. 2008-06-12 00:54:19 -04:00
Gabe Black
6b8d0363ee X86: Rename the divide count register to divide configuration. 2008-06-12 00:54:12 -04:00
Gabe Black
b10742ee2b X86: Make the apic isr and irr work. 2008-06-12 00:54:05 -04:00
Gabe Black
69000baef3 X86: Make the apic task priority register work. 2008-06-12 00:54:01 -04:00
Gabe Black
e9c481ea4a X86: Make the logical destination and destination format work. 2008-06-12 00:53:50 -04:00
Gabe Black
ed23a4970b X86: Make the apic ID register work. 2008-06-12 00:53:43 -04:00
Gabe Black
8a6723e038 X86: Make the apic version register work. 2008-06-12 00:53:37 -04:00
Gabe Black
8d2416c6e9 X86: Implement a partial, sort of correct version of the protected mode variant of iret. 2008-06-12 00:53:01 -04:00
Gabe Black
66f54a6037 X86: Change how segment loading is performed. 2008-06-12 00:52:12 -04:00
Gabe Black
129831c116 X86: Make pushes and pops use the stack size instead of the data size. 2008-06-12 00:51:57 -04:00
Gabe Black
b05299253f X86: In non 64bit mode, throw a fault when a NULL segment is accessed. 2008-06-12 00:51:50 -04:00