Commit graph

2693 commits

Author SHA1 Message Date
Ali Saidi
2609ed2a7c a bit of bad code trampling on memory
--HG--
extra : convert_revision : c0252dce6d7fc4c35ecd9f87ac4555e704de91b7
2006-04-07 16:26:22 -04:00
Ron Dreslinski
9e3d79694c Move to a model with a unified request object.
Constructor takes a bool to signify that it is either a cpu_request or not a cpu_request.
When accedding variables of a cpu_request it asserts that it is a cpu_request.
It also asserts that a value being read has been written at some point in time prior (not gaurnteeing it is up to date, but it was at least written before read).

There is also a isCpuReq() function to determine if this is a cpu_request.  It should be called before accesing a cpu_request only variable.

SConscript:
    Add compilation support for request.cc
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/io_device.cc:
mem/page_table.cc:
mem/page_table.hh:
mem/port.cc:
    Update for unified request object and accessor functions.
mem/request.hh:
    Remove CpuRequest, make it a unified object.  Make variables private with accessor functions.

    May want to move things from .cc file into header (usually a assert() and either returning a value, or writting two).

--HG--
extra : convert_revision : f1e45cc490dadc7a418634539b03c3e72684a6e3
2006-04-07 15:54:48 -04:00
Ali Saidi
6a7108897b a sparc binary that can be debugged
--HG--
extra : convert_revision : cb021c1e704b5771e0f86e794b7e59f8a4b96856
2006-04-06 18:32:10 -04:00
Ali Saidi
62ebe251da Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : a0bfc7495ba0f2916214d6712f67c5c239a210a0
2006-04-06 18:04:57 -04:00
Ali Saidi
61b2bd9d28 added unimp faults
update for newmem

arch/mips/faults.cc:
arch/mips/faults.hh:
arch/sparc/faults.cc:
arch/sparc/faults.hh:
    added unimp faults for mips
arch/mips/isa/base.isa:
arch/mips/isa/includes.isa:
    thou shalt not put includes inside a namespace
dev/alpha_console.cc:
    fix formatting
dev/io_device.hh:
    add comments
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
    update for newmem
sim/process.cc:
    fix seemingly wronge code.

--HG--
extra : convert_revision : 9dcfe188d00d525b935d8ef4fa323280bbfa9a0e
2006-04-06 18:04:49 -04:00
Gabe Black
832311a170 Fixed for full system.
--HG--
extra : convert_revision : 28c9cd55d887c9de7156c8cf76b7b91117f749d5
2006-04-06 15:21:52 -04:00
Gabe Black
bb4c2fba25 Small touchups to SPARC
arch/sparc/regfile.hh:
    Added debug output to the setAltGlobals function.

--HG--
extra : convert_revision : b5ed3ff6d6f30e840c2488d846658dadedb59869
2006-04-06 15:14:08 -04:00
Gabe Black
6a962f8343 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : bd6352647798275a12d52d55a129cdddd8e25423
2006-04-06 15:00:11 -04:00
Ali Saidi
6240f8c4bc fixes for newmem
ALPHA_FS finally compiles again

SConscript:
    Use a couple more FS sources, still don't compile that much
arch/alpha/faults.hh:
    the unimp fault should probably exist in nonfs too.
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/simconsole.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
sim/process.cc:
sim/system.cc:
    fixes for newmem
dev/io_device.hh:
    a system pointer is probably useful for every device to have
mem/bus.hh:
mem/physical.cc:
    new address ranges function
python/m5/objects/SimpleDisk.py:
    simple disk now has a system pointer rather than physmem directly

--HG--
extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
2006-04-06 14:57:51 -04:00
Gabe Black
3124c5b7bb Changed the CleanWindow fault from an enumerate fault into a regular one.
--HG--
extra : convert_revision : bf43015f5e47768a6e07ce36dc66a38426beceee
2006-04-06 14:53:14 -04:00
Gabe Black
6d8d6d15cd Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.
arch/isa_parser.py:
    Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
    Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
    Added SPARC traceflag
configs/test/hello_sparc:
    Recompiled without -mflat
cpu/cpu_exec_context.cc:
    Used the regfile clear function rather than memsetting to 0.

--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
2006-04-06 14:52:44 -04:00
Gabe Black
a4b31e8f6b Enable register windows.
arch/alpha/isa_traits.hh:
arch/mips/isa_traits.cc:
    Turned the integer register file into a class instead of a typedef to an array.
arch/alpha/regfile.hh:
    Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs.
arch/mips/isa_traits.hh:
    Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition.
arch/sparc/isa_traits.hh:
    Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger.
arch/sparc/regfile.hh:
    Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile.
cpu/cpu_exec_context.hh:
    Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0.
cpu/exec_context.hh:
    Added the changeRegFileContext function.
cpu/exetrace.cc:
    Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array.
cpu/exetrace.hh:
    Get the address of the regs object, now that it isn't an array.

--HG--
extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
2006-04-06 14:47:03 -04:00
Ali Saidi
bb80f71f21 fixes for new memory system
SConscript:
    comment out most devices
    add vport.cc
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    push in alpha name space
    fix for new memory system
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Added an unimplemented fault that can be returned if a certain
    function isn't implemented
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
arch/alpha/stacktrace.cc:
arch/alpha/system.cc:
arch/alpha/tlb.hh:
arch/alpha/tru64/system.cc:
    fixed for new memory system
arch/alpha/tlb.cc:
    fixed for new memory system
    removed code that seems to have no purpose
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    fixed for new memory system
    put in namespace AlphaISA
base/remote_gdb.cc:
    fix for new memory system
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
    create two ports one of physical accesses and one for superpage accesses
    Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically
    allocated physical or virtual ports or if an execcontext is passed in
    get a dynamically allocated virtual port
dev/alpha_console.cc:
dev/alpha_console.hh:
    Redo for new memory system
dev/io_device.cc:
dev/io_device.hh:
    new I/O devices for new memory system
kern/linux/events.cc:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
    Arguments now in namespaces
kern/tru64/tru64_events.cc:
mem/bus.cc:
    fix for new memory syste
mem/physical.hh:
    new addressranges function
    getPort should be public
mem/port.hh:
    Add write/read methods to functional port
    update getDeviceAddrRanges to have a list of both snoops and response lists
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
    Update for new mem system
sim/vptr.hh:
    comment out code and replace with panics
    This will need to be fixed at some point, but it's not easy.

--HG--
extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
2006-04-06 00:51:46 -04:00
Gabe Black
adeb458b87 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
2006-03-31 20:32:18 -05:00
Gabe Black
5c79eb0410 Fixes to SPARC for syscall emulation mode.
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
    Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
    Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
    Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
    Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
    A test program for SPARC which prints "Hello World!"

--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
2006-03-31 20:31:53 -05:00
Ali Saidi
5936c79ba0 Add a functional port that is used to load the original binaries in FS
SE mode now has a port that goes to whatever toplevel mem object the
CPU sees that does the appropriate translation for syscall emulation

SConscript:
    translating port is a syscall emu only source
arch/alpha/system.cc:
base/loader/object_file.cc:
base/loader/object_file.hh:
    Use the new functional port to write the binaries into memory
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
    We aren't always going to be writing straight to memory with syscalls
    support writing to a cache
mem/port.hh:
    Add a simple unidirectional functional port that panics on any incoming requests
mem/translating_port.hh:
    make translating port inherit from the simple port
sim/system.cc:
sim/system.hh:
    Add a functional port that is used to load the original binaries

--HG--
extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d
2006-03-30 18:06:00 -05:00
Ali Saidi
e196d20d9d Make TranslatingPort be a type of Port rather than something special
arch/alpha/arguments.cc:
    rather than returning 0, put a panic in... it will actually make us fix
    this rather than scratching our respective heads
base/loader/object_file.cc:
base/loader/object_file.hh:
    Object loader now takes a port rather than a translating port
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
sim/process.cc:
    Make translating port a type of port rather than anything special
cpu/simple/cpu.cc:
    no need to grab a port from the cpu anymore
mem/physical.cc:
    add an additional type of port to physicalmemory called "functional"
    Only used for functional accesses (loading binaries/syscall emu)
mem/port.hh:
    make readBlok/writeBlob virtual so translating port can do the
    translation first
mem/translating_port.cc:
mem/translating_port.hh:
    Make TranslatingPort inherit from Port
sim/system.cc:
    header file that doesn't exit removed

--HG--
extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
2006-03-30 15:59:49 -05:00
Kevin Lim
0b2deb2a88 Fixes for full system compiling.
arch/alpha/arguments.cc:
    There will not be a phys mem ptr in the XC in the newmem.  This read will have to go through something else.
arch/alpha/ev5.cc:
    Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used.  Also this messed up the ability to specify which CPU models are being built.
cpu/exec_context.hh:
    Remove getPhysMemPtr() function.
cpu/exetrace.cc:
    Include sim/system.hh, and sort the includes.
cpu/simple/cpu.cc:
    Fixes for full system compilation.
kern/system_events.cc:
    Remove include of encumbered FullCPU.  The branch prediction will need to be fixed up in a more generic way in the future.

--HG--
extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
2006-03-30 10:42:55 -05:00
Ali Saidi
2ad1db3fde page_table.cc is a syscall only kinda thing
fix tlbs for newmem

SConscript:
    page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    fix tlbs for newmem

--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
2006-03-29 18:42:53 -05:00
Ron Dreslinski
6f590b4ddc Fix indentation
--HG--
extra : convert_revision : 321ff3c6e8dcc41f18e983fac83e14c037081dcb
2006-03-29 17:54:58 -05:00
Ron Dreslinski
9a434869a1 Fix for prefetching check with blocking buffers. Need to look into support for prefetching with blocking buffers.
--HG--
extra : convert_revision : 7b401cf76742ffda6c911faf710970c58a0c337b
2006-03-29 17:53:52 -05:00
Gabe Black
2177d822ce Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 7866241cf43416636cbd6a3a4f6eeda561ed2e27
2006-03-29 17:40:09 -05:00
Ali Saidi
3dcb589ea4 update for connector magic
--HG--
extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58
2006-03-29 17:39:20 -05:00
Ali Saidi
35faf09bcc Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 5ab4ce9f6ec7af326d8906060ae3558cfd67ca08
2006-03-29 17:37:41 -05:00
Ali Saidi
62f5d7dd3f move stuff around so PageShift is defined before it is needed
don't ever include a file while in a namespace
start of making alpha console new memsystem happy
Make a BasePioDevice which is what all the simple Pio devices will inherit from
add a description of when the data pointer will have memory

arch/alpha/isa_traits.hh:
    don't ever include a file while in a namespace
dev/alpha_console.cc:
dev/alpha_console.hh:
    start of making alpha console new memsystem happy
dev/io_device.cc:
dev/io_device.hh:
    Make a BasePioDevice which is what all the simple Pio devices will inherit from
mem/packet.hh:
    add a description of when the data pointer will have memory

--HG--
extra : convert_revision : 495c0915541f9cad3eb42891e60b4ecbee7952bf
2006-03-29 17:37:25 -05:00
Gabe Black
1e4e989b83 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 984b015700ccef71d95b4d7d775a7b3f24084dc6
2006-03-29 17:35:51 -05:00
Kevin Lim
d46d3d6811 Remove "using namespace std" from global declarations.
--HG--
extra : convert_revision : c580bc6bd308fd502fb5a14ea84b5214e1d2718e
2006-03-29 16:05:26 -05:00
Ron Dreslinski
e881f8ce2a Add some basic statistics to the disk model
--HG--
extra : convert_revision : 0f3a45745b0122de64a2f434604a474df04f2938
2006-03-29 14:27:10 -05:00
Steve Reinhardt
c5c76cea98 Make CPU_MODELS a sticky build option.
This causes a crash if you're using scons 0.96.1 *and* you specify
more than one CPU model.  Since the .isa scanner now works with 0.96.91
then upgrading should not be an issue.  For now we're only using one CPU
model (SimpleCPU) so there isn't even a pressing need to upgrade yet.

build/SConstruct:
    Make CPU_MODELS a sticky option.
    This causes a crash if you're using scons 0.96.1 *and* you specify
    more than one CPU model.  Since the .isa scanner now works with 0.96.91
    then upgrading should not be an issue.  For now we're only using one CPU
    model (SimpleCPU) so there isn't even a pressing need to upgrade yet.

--HG--
extra : convert_revision : d8319c4cd5c937c2c033270cef850d19b805d256
2006-03-28 22:55:08 -05:00
Steve Reinhardt
ce7f076a83 Only compile in Tru64 objects if we're doing Alpha.
--HG--
extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-28 22:44:24 -05:00
Steve Reinhardt
5f307ebe35 Use op_decl instead of op_src_decl + op_dest_decl in .isa templates.
The latter causes multiple variable definitions if the same operand
is used as both a src and a dest.

arch/alpha/isa/mem.isa:
arch/mips/isa/formats/mem.isa:
    Use op_decl instead of op_src_decl + op_dest_decl.
    The latter causes multiple variable definitions if the same operand
    is used as both a src and a dest.

--HG--
extra : convert_revision : c14d91b293d3afef45c8728d3d8784f372c0b7f4
2006-03-28 22:32:08 -05:00
Steve Reinhardt
59b3987cc4 Make Alpha ItbFault methods abstract instead of calling panic()
(which wasn't working since panic() isn't declared yet here).

arch/alpha/faults.hh:
    Make ItbFault methods abstract instead of calling panic()
    (which wasn't working since panic() isn't declared yet here).

--HG--
extra : convert_revision : b15242baa370777f265a3f6b7d5f5c05702b016f
2006-03-28 22:30:43 -05:00
Steve Reinhardt
efc41fe82d Make .isa-file ##include file paths relative to including file.
Makes .isa files cleaner and simplifies scanner too.
Simplified scanner to work under both old and new versions of scons.

arch/SConscript:
    Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now.
    Assumes .isa ##include paths are relative to including file.
arch/alpha/isa/main.isa:
arch/mips/isa/formats/formats.isa:
arch/mips/isa/main.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
    Make ##include paths relative to including file.
arch/isa_parser.py:
    Make ##include file paths relative to including file.
    Makes .isa files cleaner and simplifies scanner too.
    Partial rewrite of include-handling code to use cool re.sub() feature
    where you can specify a function to provide the replacement string.
    Minor cleanup of error-handling code.
    Also got rid of '#!' at top to make caller choose which python interpreter
    is used (since SPARC now requires 2.4 to build, we may need to do that via
    scons in the future).

--HG--
rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa
extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
2006-03-28 22:29:42 -05:00
Gabe Black
76daf50937 Fixed a typo.
--HG--
extra : convert_revision : 9ad2bde341a9efb2826159229427b719ff2142f4
2006-03-28 19:39:29 -05:00
Gabe Black
55293c9e98 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 7effd744f9061d4aa8e9c3fa769115dfa73cbb79
2006-03-28 19:36:40 -05:00
Gabe Black
818f3ae22f SPARC compiles for SE!
arch/sparc/isa/decoder.isa:
    Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
    Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
    Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
    Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
    Changed regSpace to have the correct size.
arch/sparc/utility.hh:
    A new file for sparc to match the one for alpha.

--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
2006-03-28 19:36:34 -05:00
Kevin Lim
c1046488e0 Move TLB faults into the normal Fault code. The TLB no longer fills in IPRs through its own fault() method; this is handled by the fault's invoke() methods.
arch/alpha/faults.cc:
    Move TLB fault code into the normal fault invoke() method.
arch/alpha/faults.hh:
    Move DTB/ITB fault handling code into their own class with a specific invoke() method.  Have DTB/ITB faults derive from these classes.

    Unfortunately the DtbAlignmentFault is somewhat odd; it's a normal alignment fault, but it must also set some specific IPRs.
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    Setting IPRs is now handled through the fault itself.

--HG--
extra : convert_revision : 5cb92ce2186ff79f632bfcbc9ba62a8a04400eae
2006-03-28 18:01:01 -05:00
Gabe Black
1507bfb20a Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 762df7bf15e8e22a8fab8bbcd933047d1c8cdfa9
2006-03-28 15:14:13 -05:00
Gabe Black
7abba53747 Moving towards compilation.
arch/sparc/isa/decoder.isa:
    Fixed comments so they don't comment out the ending braces of the format specifier.

--HG--
extra : convert_revision : 3f037c0a17abd0dff71d22fdcd95959c3670e88a
2006-03-28 15:13:57 -05:00
Ron Dreslinski
9e39454f58 Make the .mpy file a .py file and convert it to the form recognized now.
--HG--
extra : convert_revision : 1019fd1e2bb484e1ea8f15db8dbe8e7a0201bd58
2006-03-28 14:58:23 -05:00
Ron Dreslinski
cdd861084a Add the detailed DRAM model into M5. See the /mem/timing/DRAM_M5.txt for discussion on setting paramaters.
SConscript:
    Add support for detailed DRAM model

--HG--
extra : convert_revision : b65f9a810fa95957b585c85632ac20f9283337d1
2006-03-27 15:06:16 -05:00
Ali Saidi
c27c122afc Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-26 21:44:22 -05:00
Ali Saidi
4973a16b34 update for objects having a bus
--HG--
extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
2006-03-25 18:34:50 -05:00
Ali Saidi
b38f67d5b7 Implement a very very simple bus
requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-25 18:31:20 -05:00
Ron Dreslinski
b96405b7e4 Add support in the fullsys script to run the POVray benchmark.
To run it use
-ETEST=POVRAY_BENCH   to run the built in povray benchmark program (more CPU intensive, small fileset ~11MB)
-ETEST=POVRAY_AUTUMN  to run the first part of a rendering of a autumn leaves/tree scene, less cpu intensive ~500MB working set.

For now I have been running with -ESYSTEM=Simple in order to drop checkpoints (built into binary at the point the render begins) and create memory traces.
I will check in a SYSTEM=3D_DRAM and SYSTEM=3D_CACHE configuration as soon as those are ready.

--HG--
extra : convert_revision : fb55834a02317d5e9961a5145c932965c8bc6a0e
2006-03-23 18:05:39 -05:00
Ali Saidi
a70ce910f3 Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 45dba22ecbdfc8e1bb0df1efd06a37f40d56b67f
2006-03-21 15:45:40 -05:00
Ali Saidi
8654cfa427 Make PioPort/DmaPort,DmaDevice/PioDevice compile.
Add another type to the PacketResult enum of Unknown
Seperate time into requsetTime and responseTime.

dev/io_device.cc:
dev/io_device.hh:
    Make PioPort/DmaPort,DmaDevice/PioDevice compile.
mem/packet.hh:
    Add another type to the PacketResult enum of Unknown (e.g. no state set yet)
mem/request.hh:
    Seperate time into requsetTime and responseTime.

--HG--
extra : convert_revision : c6394cb838013296caea6492275252b8cae2882f
2006-03-21 15:45:31 -05:00
Korey Sewell
b855ea6968 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips

--HG--
extra : convert_revision : db8490e41ec17fc8f4e2dc9548ecdc7d28b4cdd1
2006-03-19 13:41:04 -05:00
Korey Sewell
b3464ef180 support for unaligned memory access
arch/mips/isa/base.isa:
    disassembly fixes
arch/mips/isa/decoder.isa:
    support for unaligned loads/stores
arch/mips/isa_traits.hh:
    edit Syscall Reg values
arch/mips/linux_process.cc:
    call writevFunc on writev syscall

--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
2006-03-19 13:40:03 -05:00
Steve Reinhardt
c1006e429d Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

sim/process.cc:
    Fix bad auto merge (m5 changes unnecessary in newmem).

--HG--
extra : convert_revision : a3ced4cd1668cd47bd02430872ca68b1433aae98
2006-03-18 14:42:21 -05:00