Daniel Johnson
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09a6e424ec
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ARM: Implement numcpus bits in L2CTLR register.
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2011-09-13 12:06:13 -05:00 |
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Ali Saidi
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d63020717c
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ARM: Adds dummy support for a L2 latency miscreg.
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2011-02-23 15:10:48 -06:00 |
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Matt Horsnell
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adbd84ab9f
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ARM: The ARM decoder should not panic when decoding undefined holes is arch.
This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
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2011-01-18 16:30:05 -06:00 |
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Ali Saidi
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38cf6a164d
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ARM: Implement some more misc registers
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2010-08-23 11:18:40 -05:00 |
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Ali Saidi
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c1e1de8d69
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ARM: Some TLB bug fixes.
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2010-06-02 12:58:16 -05:00 |
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Ali Saidi
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7de7ea3b22
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ARM: Move Miscreg functions out of isa.hh
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2010-06-02 12:58:16 -05:00 |
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Ali Saidi
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cb9936cfde
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ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
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2010-06-02 12:58:16 -05:00 |
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Gabe Black
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b5cfa9361b
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ARM: Convert the CP15 registers from MPU to MMU.
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2010-06-02 12:58:13 -05:00 |
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Gabe Black
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6aa229386d
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ARM: Implement a function to decode CP15 registers to MiscReg indices.
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2010-06-02 12:58:08 -05:00 |
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