ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.
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@ -71,39 +71,7 @@ format DataOp {
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0: ArmDataProcReg::armDataProcReg();
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0: ArmDataProcReg::armDataProcReg();
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1: decode OPCODE_7 {
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1: decode OPCODE_7 {
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0x0: decode MISC_OPCODE {
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0x0: decode MISC_OPCODE {
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0x0: decode OPCODE {
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0x0: ArmMsrMrs::armMsrMrs();
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0x8: PredOp::mrs_cpsr({{
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Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
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}});
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0x9: decode USEIMM {
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// The mask field is the same as the RN index.
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0: PredOp::msr_cpsr_reg({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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Rm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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1: PredImmOp::msr_cpsr_imm({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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rotated_imm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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}
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0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
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0xb: decode USEIMM {
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// The mask field is the same as the RN index.
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0: PredOp::msr_spsr_reg({{
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Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
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}});
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1: PredImmOp::msr_spsr_imm({{
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Spsr = spsrWriteByInstr(Spsr, rotated_imm,
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RN, false);
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}});
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}
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}
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0x1: decode OPCODE {
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0x1: decode OPCODE {
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0x9: ArmBx::armBx();
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0x9: ArmBx::armBx();
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0xb: PredOp::clz({{
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0xb: PredOp::clz({{
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@ -40,3 +40,40 @@
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def format Svc() {{
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def format Svc() {{
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decode_block = "return new Svc(machInst);"
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decode_block = "return new Svc(machInst);"
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}};
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}};
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def format ArmMsrMrs() {{
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decode_block = '''
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{
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const uint8_t byteMask = bits(machInst, 19, 16);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
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const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const uint32_t opcode = bits(machInst, 24, 21);
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const bool useImm = bits(machInst, 25);
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const uint32_t unrotated = bits(machInst, 7, 0);
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const uint32_t rotation = (bits(machInst, 11, 8) << 1);
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const uint32_t imm = rotate_imm(unrotated, rotation);
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switch (opcode) {
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case 0x8:
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return new MrsCpsr(machInst, rd);
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case 0x9:
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if (useImm) {
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return new MsrCpsrImm(machInst, imm, byteMask);
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} else {
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return new MsrCpsrReg(machInst, rn, byteMask);
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}
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case 0xa:
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return new MrsSpsr(machInst, rd);
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case 0xb:
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if (useImm) {
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return new MsrSpsrImm(machInst, imm, byteMask);
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} else {
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return new MsrSpsrReg(machInst, rn, byteMask);
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}
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default:
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return new Unknown(machInst);
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}
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}
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'''
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}};
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