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Some hand merges

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--HG--
rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy
extra : convert_revision : b24ff4c1feb480cf280207d4bbdfe08ef80d1aa2
This commit is contained in:
Ron Dreslinski 2005-04-01 19:39:23 -05:00
commit fdceb0f00c
3 changed files with 15 additions and 1 deletions
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4
SConscript
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@ -165,6 +165,10 @@ base_sources = Split('''
mem/cache/miss/miss_queue.cc mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc mem/cache/miss/mshr_queue.cc
mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/stride_prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc mem/cache/tags/base_tags.cc
mem/cache/tags/cache_tags.cc mem/cache/tags/cache_tags.cc
mem/cache/tags/fa_lru.cc mem/cache/tags/fa_lru.cc

3
base/traceflags.py
View file

@ -123,7 +123,8 @@ baseFlags = [
'Uart', 'Uart',
'Split', 'Split',
'SQL', 'SQL',
'Thread' 'Thread',
'HWPrefetch'
] ]
# #

9
python/m5/objects/BaseCache.mpy
View file

@ -36,3 +36,12 @@ simobj BaseCache(BaseMem):
two_queue = Param.Bool(False, two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement") "whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers") write_buffers = Param.Int(8, "number of write buffers")
prefetch_miss = Param.Bool(False,
"wheter you are using the hardware prefetcher from Miss stream")
prefetch_access = Param.Bool(False,
"wheter you are using the hardware prefetcher from Access stream")
prefetcher_size = Param.Int(100,
"Number of entries in the harware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")