diff --git a/SConscript b/SConscript
index 93962778f..7f9e56f70 100644
--- a/SConscript
+++ b/SConscript
@@ -165,6 +165,10 @@ base_sources = Split('''
 	mem/cache/miss/miss_queue.cc
 	mem/cache/miss/mshr.cc
 	mem/cache/miss/mshr_queue.cc
+        mem/cache/prefetch/base_prefetcher.cc
+        mem/cache/prefetch/prefetcher.cc
+        mem/cache/prefetch/stride_prefetcher.cc
+        mem/cache/prefetch/tagged_prefetcher.cc
 	mem/cache/tags/base_tags.cc
 	mem/cache/tags/cache_tags.cc
 	mem/cache/tags/fa_lru.cc
diff --git a/base/traceflags.py b/base/traceflags.py
index 800c47bd3..74b87e1b9 100644
--- a/base/traceflags.py
+++ b/base/traceflags.py
@@ -123,7 +123,8 @@ baseFlags = [
     'Uart',
     'Split',
     'SQL',
-    'Thread'
+    'Thread',
+    'HWPrefetch'
     ]
 
 #
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
index b9986917f..198665325 100644
--- a/python/m5/objects/BaseCache.mpy
+++ b/python/m5/objects/BaseCache.mpy
@@ -36,3 +36,12 @@ simobj BaseCache(BaseMem):
     two_queue = Param.Bool(False,
         "whether the lifo should have two queue replacement")
     write_buffers = Param.Int(8, "number of write buffers")
+    prefetch_miss = Param.Bool(False,
+         "wheter you are using the hardware prefetcher from Miss stream")
+    prefetch_access = Param.Bool(False,
+         "wheter you are using the hardware prefetcher from Access stream")
+    prefetcher_size = Param.Int(100,
+         "Number of entries in the harware prefetch queue")
+    prefetch_past_page = Param.Bool(False,
+         "Allow prefetches to cross virtual page boundaries")
+