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Stats: Updates due to bus changes

Browse source 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
This commit is contained in:
Andreas Hansson 2012-07-09 12:35:41 -04:00
parent b265d9925c
commit fda338f8d3
249 changed files with 34082 additions and 34090 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -941,7 +941,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=true use_default_range=true
width=64 width=8
default=system.tsunami.pciconfig.pio default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@ -1003,7 +1003,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0] master=system.bridge.slave system.physmem.port[0]
slave=system.system_port system.iocache.mem_side system.l2c.mem_side slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@ -1060,7 +1060,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:47:55 gem5 started Jul 2 2012 11:07:21
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 106801000 info: Launching CPU 1 @ 112168000
Exiting @ tick 1896395899500 because m5_exit instruction encountered Exiting @ tick 1900530800500 because m5_exit instruction encountered

3016
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -517,7 +517,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=true use_default_range=true
width=64 width=8
default=system.tsunami.pciconfig.pio default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@ -579,7 +579,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0] master=system.bridge.slave system.physmem.port[0]
slave=system.system_port system.iocache.mem_side system.l2c.mem_side slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@ -636,7 +636,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:47:37 gem5 started Jul 2 2012 11:00:25
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1858879782500 because m5_exit instruction encountered Exiting @ tick 1865402113500 because m5_exit instruction encountered

1514
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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File diff suppressed because it is too large Load diff

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
memories=system.realview.nvmem system.physmem memories=system.physmem system.realview.nvmem
midr_regval=890224640 midr_regval=890224640
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
@ -577,7 +577,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
@ -638,7 +638,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@ -1051,7 +1051,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port

28
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -10,25 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr icimvau' unimplemented
warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported warn: LCD dual screen mode not supported
warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr bpiallis' unimplemented
warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 01:32:52 gem5 started Jul 2 2012 17:05:39
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2500827052500 because m5_exit instruction encountered Exiting @ tick 2502549875500 because m5_exit instruction encountered

1598
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
memories=system.physmem system.realview.nvmem memories=system.realview.nvmem system.physmem
midr_regval=890224640 midr_regval=890224640
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
@ -960,7 +960,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
@ -1021,7 +1021,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@ -1434,7 +1434,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port

1
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -14,7 +14,6 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis
warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 01:33:16 gem5 started Jul 2 2012 17:16:08
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2569716290500 because m5_exit instruction encountered Exiting @ tick 2581527583500 because m5_exit instruction encountered

2964
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
memories=system.realview.nvmem system.physmem memories=system.physmem system.realview.nvmem
midr_regval=890224640 midr_regval=890224640
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
@ -518,7 +518,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
@ -579,7 +579,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@ -992,7 +992,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 01:31:55 gem5 started Jul 2 2012 17:04:56
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2500827052500 because m5_exit instruction encountered Exiting @ tick 2502549875500 because m5_exit instruction encountered

1568
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -935,7 +935,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=true use_default_range=true
width=64 width=8
default=system.pc.pciconfig.pio default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
@ -997,7 +997,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
default=system.membus.badaddr_responder.pio default=system.membus.badaddr_responder.pio
master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
@ -1477,7 +1477,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.l2c.cpu_side master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 29 2012 00:25:59 gem5 started Jul 2 2012 14:54:43
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5147413032500 because m5_exit instruction encountered Exiting @ tick 5173840734500 because m5_exit instruction encountered

1782
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -1190,7 +1190,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=true use_default_range=true
width=64 width=8
default=system.pc.pciconfig.pio default=system.pc.pciconfig.pio
master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master

9
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,13 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:12 gem5 compiled Jul 2 2012 09:03:01
gem5 started Jun 4 2012 17:11:29 gem5 started Jul 2 2012 15:09:17
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
warning: add_child('terminal'): child 'terminal' already has parent warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5304689685500 because m5_exit instruction encountered Exiting @ tick 5305568291500 because m5_exit instruction encountered

192
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -1,77 +1,77 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 5.304690 # Number of seconds simulated sim_seconds 5.305568 # Number of seconds simulated
sim_ticks 5304689685500 # Number of ticks simulated sim_ticks 5305568291500 # Number of ticks simulated
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5305568291500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 163049 # Simulator instruction rate (inst/s) host_inst_rate 254586 # Simulator instruction rate (inst/s)
host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) host_op_rate 522269 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6301127704 # Simulator tick rate (ticks/s) host_tick_rate 9722568027 # Simulator tick rate (ticks/s)
host_mem_usage 481488 # Number of bytes of host memory used host_mem_usage 466304 # Number of bytes of host memory used
host_seconds 841.86 # Real time elapsed on the host host_seconds 545.70 # Real time elapsed on the host
sim_insts 137264752 # Number of instructions simulated sim_insts 138926459 # Number of instructions simulated
sim_ops 280412254 # Number of ops (including micro ops) simulated sim_ops 285000258 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 843624624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 40107648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 468878472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 53485285 # Number of bytes read from this memory
system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory system.physmem.bytes_read::total 1406463005 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 843624624 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 468878472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1312503096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 32434308 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 35512736 # Number of bytes written to this memory
system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory system.physmem.bytes_written::total 70938164 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 105453078 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 6721984 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 58609809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 8980290 # Number of read requests responded to by this memory
system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory system.physmem.num_reads::total 179807449 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4872641 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 4951979 # Number of write requests responded to by this memory
system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory system.physmem.num_writes::total 9871358 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 159007401 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 7559539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 88374788 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 10080972 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 265091867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 159007401 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 88374788 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 247382189 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6113258 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 6693484 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 13370512 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 159007401 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 13672797 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 88374788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 16774456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 278462379 # Total bandwidth to/from this memory (bytes/s)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
@ -84,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.numCycles 10608177450 # number of cpu cycles simulated system.cpu0.numCycles 10611136583 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 88690468 # Number of instructions committed system.cpu0.committedInsts 90467543 # Number of instructions committed
system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed system.cpu0.committedOps 191745753 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses system.cpu0.num_int_alu_accesses 172320951 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured system.cpu0.num_func_calls 0 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls system.cpu0.num_conditional_control_insts 18433460 # number of instructions that are conditional controls
system.cpu0.num_int_insts 168469813 # number of integer instructions system.cpu0.num_int_insts 172320951 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read system.cpu0.num_int_register_reads 529440727 # number of times the integer registers were read
system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written system.cpu0.num_int_register_writes 286411795 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 19132508 # number of memory refs system.cpu0.num_mem_refs 19683524 # number of memory refs
system.cpu0.num_load_insts 14284566 # Number of load instructions system.cpu0.num_load_insts 14800104 # Number of load instructions
system.cpu0.num_store_insts 4847942 # Number of store instructions system.cpu0.num_store_insts 4883420 # Number of store instructions
system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles system.cpu0.num_idle_cycles 10087380547.886099 # Number of idle cycles
system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles system.cpu0.num_busy_cycles 523756035.113901 # Number of busy cycles
system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.numCycles 10609379371 # number of cpu cycles simulated system.cpu1.numCycles 10608184508 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 48574284 # Number of instructions committed system.cpu1.committedInsts 48458916 # Number of instructions committed
system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed system.cpu1.committedOps 93254505 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses system.cpu1.num_int_alu_accesses 88898001 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured system.cpu1.num_func_calls 0 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls system.cpu1.num_conditional_control_insts 8156206 # number of instructions that are conditional controls
system.cpu1.num_int_insts 89110416 # number of integer instructions system.cpu1.num_int_insts 88898001 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read system.cpu1.num_int_register_reads 272266493 # number of times the integer registers were read
system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written system.cpu1.num_int_register_writes 138281277 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 14426742 # number of memory refs system.cpu1.num_mem_refs 14383510 # number of memory refs
system.cpu1.num_load_insts 9181010 # Number of load instructions system.cpu1.num_load_insts 9129721 # Number of load instructions
system.cpu1.num_store_insts 5245732 # Number of store instructions system.cpu1.num_store_insts 5253789 # Number of store instructions
system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles system.cpu1.num_idle_cycles 10274260882.632458 # Number of idle cycles
system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles system.cpu1.num_busy_cycles 333923625.367543 # Number of busy cycles
system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed

4
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -181,7 +181,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -213,7 +213,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:10:24 gem5 started Jul 2 2012 09:09:56
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 271948359500 because target called exit() Exiting @ tick 274137499500 because target called exit()

554
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.271948 # Number of seconds simulated sim_seconds 0.274137 # Number of seconds simulated
sim_ticks 271948359500 # Number of ticks simulated sim_ticks 274137499500 # Number of ticks simulated
final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167086 # Simulator instruction rate (inst/s) host_inst_rate 167497 # Simulator instruction rate (inst/s)
host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) host_op_rate 167497 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 75497413 # Simulator tick rate (ticks/s) host_tick_rate 76292716 # Simulator tick rate (ticks/s)
host_mem_usage 219024 # Number of bytes of host memory used host_mem_usage 218988 # Number of bytes of host memory used
host_seconds 3602.09 # Real time elapsed on the host host_seconds 3593.23 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517207 # DTB read hits system.cpu.dtb.read_hits 114518785 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114519838 # DTB read accesses system.cpu.dtb.read_accesses 114521416 # DTB read accesses
system.cpu.dtb.write_hits 39661898 # DTB write hits system.cpu.dtb.write_hits 39662429 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39664200 # DTB write accesses system.cpu.dtb.write_accesses 39664731 # DTB write accesses
system.cpu.dtb.data_hits 154179105 # DTB hits system.cpu.dtb.data_hits 154181214 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154184038 # DTB accesses system.cpu.dtb.data_accesses 154186147 # DTB accesses
system.cpu.itb.fetch_hits 25013413 # ITB hits system.cpu.itb.fetch_hits 25086764 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25013435 # ITB accesses system.cpu.itb.fetch_accesses 25086786 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 543896720 # number of cpu cycles simulated system.cpu.numCycles 548275000 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155049936 # Number of Address Generations system.cpu.agen_unit.agens 155050348 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed.
system.cpu.activity 89.936283 # Percentage of cycles cpu is active system.cpu.activity 89.213772 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads
system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use
system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits
system.cpu.icache.overall_hits::total 25012389 # number of overall hits system.cpu.icache.overall_hits::total 25085741 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
system.cpu.icache.overall_misses::total 1022 # number of overall misses system.cpu.icache.overall_misses::total 1021 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use
system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits
system.cpu.dcache.overall_hits::total 152406141 # number of overall hits system.cpu.dcache.overall_hits::total 152406041 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses
system.cpu.dcache.overall_misses::total 1559222 # number of overall misses system.cpu.dcache.overall_misses::total 1559322 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 917 # number of replacements system.cpu.l2cache.replacements 917 # number of replacements
system.cpu.l2cache.tagsinuse 22852.415153 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538842 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.284159 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21652.224350 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.469676 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 480.721127 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660773 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021956 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014670 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697400 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197093 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197107 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232986 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232986 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44029000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214315000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 258344000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1104963500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1104963500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44029000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1319278500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1363307500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44029000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1319278500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1363307500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024551 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083389 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083389 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 766500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9462.962963 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33775500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198626500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 849849500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 849849500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33775500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014700500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1048476000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

4
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -479,7 +479,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -511,7 +511,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:10:29 gem5 started Jul 2 2012 09:10:10
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 133563007500 because target called exit() Exiting @ tick 135504709500 because target called exit()

1138
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -148,7 +148,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -180,7 +180,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:10:37 gem5 started Jul 2 2012 09:11:02
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 762853846000 because target called exit() Exiting @ tick 764109115000 because target called exit()

188
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.762854 # Number of seconds simulated sim_seconds 0.764109 # Number of seconds simulated
sim_ticks 762853846000 # Number of ticks simulated sim_ticks 764109115000 # Number of ticks simulated
final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2331221 # Simulator instruction rate (inst/s) host_inst_rate 2465110 # Simulator instruction rate (inst/s)
host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2954822927 # Simulator tick rate (ticks/s) host_tick_rate 3129668646 # Simulator tick rate (ticks/s)
host_mem_usage 219024 # Number of bytes of host memory used host_mem_usage 218984 # Number of bytes of host memory used
host_seconds 258.17 # Real time elapsed on the host host_seconds 244.15 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu
system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory
system.physmem.num_writes::total 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 1525707692 # number of cpu cycles simulated system.cpu.numCycles 1528218230 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed system.cpu.committedInsts 601856964 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu
system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1525707692 # Number of busy cycles system.cpu.num_busy_cycles 1528218230 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
system.cpu.icache.overall_misses::total 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
system.cpu.dcache.overall_misses::total 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.replacements 903 # number of replacements
system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21648.658638 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 668.310399 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 525.032413 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660665 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.020395 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016023 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697083 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits

4
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -497,7 +497,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -529,7 +529,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:37:13 gem5 started Jul 2 2012 15:22:13
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 163291004000 because target called exit() Exiting @ tick 164812294500 because target called exit()

1112
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -166,7 +166,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -198,7 +198,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:38:23 gem5 started Jul 2 2012 15:28:47
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 794147534000 because target called exit() Exiting @ tick 795270546000 because target called exit()

186
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.794148 # Number of seconds simulated sim_seconds 0.795271 # Number of seconds simulated
sim_ticks 794147534000 # Number of ticks simulated sim_ticks 795270546000 # Number of ticks simulated
final_tick 794147534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1549107 # Simulator instruction rate (inst/s) host_inst_rate 873454 # Simulator instruction rate (inst/s)
host_op_rate 1635914 # Simulator op (including micro ops) rate (op/s) host_op_rate 922399 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2163825213 # Simulator tick rate (ticks/s) host_tick_rate 1221783566 # Simulator tick rate (ticks/s)
host_mem_usage 232760 # Number of bytes of host memory used host_mem_usage 232680 # Number of bytes of host memory used
host_seconds 367.01 # Real time elapsed on the host host_seconds 650.91 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 27110 # Nu
system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory
system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49240 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 49171 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2184783 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2181698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2234023 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2230868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49240 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 49171 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49240 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 49171 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 245234 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 244888 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 245234 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 244888 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 245234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 244888 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49240 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 49171 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2184783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2181698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2479257 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2475756 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1588295068 # number of cpu cycles simulated system.cpu.numCycles 1590541092 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 568539335 # Number of instructions committed system.cpu.committedInsts 568539335 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 219173606 # nu
system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_load_insts 148952593 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1588295068 # Number of busy cycles system.cpu.num_busy_cycles 1590541092 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 577.753136 # Cycle average of tags in use system.cpu.icache.tagsinuse 577.715333 # Cycle average of tags in use
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 577.753136 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 577.715333 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.282106 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.282088 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.282106 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.282088 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
system.cpu.icache.overall_misses::total 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34664000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 34792000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34664000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 34792000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34664000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 34792000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34664000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 34792000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34664000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 34792000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34664000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 34792000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53909.797823 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 54108.864697 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53909.797823 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54108.864697 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32863000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 32863000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32863000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 32863000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32863000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32863000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.217417 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4094.191707 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 536853000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 547974000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.217417 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4094.191707 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999565 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999559 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999565 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999559 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2865114000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 2866972000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2865114000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2866972000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4399402000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4400884000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4399402000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4400884000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7264516000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 7267856000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7264516000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 7267856000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7264516000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7267856000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7264516000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7267856000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16602.179338 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 16609.812507 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16602.179338 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 16609.812507 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295666000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2297524000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295666000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2297524000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3657640000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3657640000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5951824000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5955164000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5951824000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 5955164000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5951824000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5955164000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5951824000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5955164000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 3963 # number of replacements system.cpu.l2cache.replacements 3963 # number of replacements
system.cpu.l2cache.tagsinuse 21581.956920 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 21579.150724 # Cycle average of tags in use
system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20942.700989 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 20939.895204 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 130.076740 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 130.071130 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 509.179191 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 509.184390 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.639121 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.639035 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.003969 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.658629 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.658543 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits

4
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -479,7 +479,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -511,7 +511,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:06:58 gem5 compiled Jul 2 2012 08:54:18
gem5 started Jun 28 2012 22:54:22 gem5 started Jul 2 2012 11:32:18
gem5 executing on zizzer gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 387353399000 because target called exit() Exiting @ tick 389181871500 because target called exit()

1018
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -148,7 +148,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -180,7 +180,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:06:58 gem5 compiled Jul 2 2012 08:54:18
gem5 started Jun 28 2012 22:54:27 gem5 started Jul 2 2012 12:13:11
gem5 executing on zizzer gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 2061521023000 because target called exit() Exiting @ tick 2063177751000 because target called exit()

188
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 2.061521 # Number of seconds simulated sim_seconds 2.063178 # Number of seconds simulated
sim_ticks 2061521023000 # Number of ticks simulated sim_ticks 2063177751000 # Number of ticks simulated
final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2065708 # Simulator instruction rate (inst/s) host_inst_rate 1349558 # Simulator instruction rate (inst/s)
host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s) host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2867468443 # Simulator tick rate (ticks/s) host_tick_rate 1874864984 # Simulator tick rate (ticks/s)
host_mem_usage 221124 # Number of bytes of host memory used host_mem_usage 222108 # Number of bytes of host memory used
host_seconds 718.93 # Real time elapsed on the host host_seconds 1100.44 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26134 # Nu
system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 31858 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 810680 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 842537 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 31858 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 31858 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 78264 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 78264 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 78264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 31858 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4123042046 # number of cpu cycles simulated system.cpu.numCycles 4126355502 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108101 # Number of instructions committed system.cpu.committedInsts 1485108101 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu
system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4123042046 # Number of busy cycles system.cpu.num_busy_cycles 4126355502 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
system.cpu.icache.overall_misses::total 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 58777000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 58777000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 58777000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 53095.754291 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 53095.754291 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55456000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 55456000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55456000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 55456000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55456000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 55456000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
system.cpu.dcache.overall_misses::total 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888728000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2888728000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554574000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4554574000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 16423.371741 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 16423.371741 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2308270000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2308270000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6083660000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 6083660000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6083660000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6083660000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2614 # number of replacements system.cpu.l2cache.replacements 2614 # number of replacements
system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use
system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20830.127393 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 857.488075 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 499.254810 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.635685 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.026168 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015236 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.677090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.677044 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits

4
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -532,7 +532,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

7
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:06:37 gem5 started Jul 2 2012 12:44:41
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -24,6 +24,7 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Compressing Input Data, level 5 Compressing Input Data, level 5
info: Increasing stack size by one page.
Compressed data 83382 bytes in length Compressed data 83382 bytes in length
Uncompressing Data Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
@ -39,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 636762784500 because target called exit() Exiting @ tick 636963896500 because target called exit()

986
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -169,7 +169,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -201,7 +201,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

6
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:10:36 gem5 started Jul 2 2012 13:03:08
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 1800635309000 because target called exit() Exiting @ tick 1801979727000 because target called exit()

186
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 1.800635 # Number of seconds simulated sim_seconds 1.801980 # Number of seconds simulated
sim_ticks 1800635309000 # Number of ticks simulated sim_ticks 1801979727000 # Number of ticks simulated
final_tick 1800635309000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1801979727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 904173 # Simulator instruction rate (inst/s) host_inst_rate 622629 # Simulator instruction rate (inst/s)
host_op_rate 1665987 # Simulator op (including micro ops) rate (op/s) host_op_rate 1147227 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1850044030 # Simulator tick rate (ticks/s) host_tick_rate 1274922997 # Simulator tick rate (ticks/s)
host_mem_usage 228536 # Number of bytes of host memory used host_mem_usage 228496 # Number of bytes of host memory used
host_seconds 973.29 # Real time elapsed on the host host_seconds 1413.40 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26287 # Nu
system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25662 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 25643 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 934319 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 933622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 959981 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 959265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25662 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 25643 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25662 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 25643 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 89213 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 89146 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 89213 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 89146 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 89213 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 89146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25662 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 25643 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049194 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3601270618 # number of cpu cycles simulated system.cpu.numCycles 3603959454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025313 # Number of instructions committed system.cpu.committedInsts 880025313 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228182 # nu
system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3601270618 # Number of busy cycles system.cpu.num_busy_cycles 3603959454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.189072 # Cycle average of tags in use system.cpu.icache.tagsinuse 660.169533 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.189072 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 660.169533 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322358 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322358 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
system.cpu.icache.overall_misses::total 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 40521000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 40521000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 40521000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 56123.268698 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56123.268698 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38355000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 38355000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38355000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 38355000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38355000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38355000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.895332 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4094.884021 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 788858000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.895332 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4094.884021 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999730 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999730 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
system.cpu.dcache.overall_misses::total 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2943878000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 2948308000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2943878000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2948308000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4348848000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4362877000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4348848000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4362877000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7292726000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7292726000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7292726000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7292726000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16497.588497 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 16539.346406 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16497.588497 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 16539.346406 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2356330000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2356330000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3614682000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3628711000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3614682000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3628711000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5966582000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5985041000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5966582000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 5985041000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5966582000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5985041000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5966582000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5985041000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2581 # number of replacements system.cpu.l2cache.replacements 2581 # number of replacements
system.cpu.l2cache.tagsinuse 22163.019096 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22161.849584 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21019.596332 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 21018.400125 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 596.850673 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 596.832039 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.572092 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 546.617420 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641467 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016680 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.676362 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.676326 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits

4
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -497,7 +497,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -529,7 +529,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:41:22 gem5 started Jul 2 2012 15:39:45
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 25878583500 because target called exit() Exiting @ tick 28553466500 because target called exit()

1144
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -166,7 +166,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -198,7 +198,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:44:41 gem5 started Jul 2 2012 15:40:44
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 148083373000 because target called exit() Exiting @ tick 148267705000 because target called exit()

180
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.148083 # Number of seconds simulated sim_seconds 0.148268 # Number of seconds simulated
sim_ticks 148083373000 # Number of ticks simulated sim_ticks 148267705000 # Number of ticks simulated
final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1433979 # Simulator instruction rate (inst/s) host_inst_rate 1021914 # Simulator instruction rate (inst/s)
host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s) host_op_rate 1029241 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2344399916 # Simulator tick rate (ticks/s) host_tick_rate 1672798092 # Simulator tick rate (ticks/s)
host_mem_usage 365828 # Number of bytes of host memory used host_mem_usage 365748 # Number of bytes of host memory used
host_seconds 63.16 # Real time elapsed on the host host_seconds 88.63 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 296166746 # number of cpu cycles simulated system.cpu.numCycles 296535410 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576861 # Number of instructions committed system.cpu.committedInsts 90576861 # Number of instructions committed
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu
system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_load_insts 22573966 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 296166746 # Number of busy cycles system.cpu.num_busy_cycles 296535410 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use
system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits

4
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -148,7 +148,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -180,7 +180,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:06:58 gem5 compiled Jul 2 2012 08:54:18
gem5 started Jun 28 2012 22:55:42 gem5 started Jul 2 2012 12:31:43
gem5 executing on zizzer gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 362428997000 because target called exit() Exiting @ tick 362481577000 because target called exit()

194
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.362429 # Number of seconds simulated sim_seconds 0.362482 # Number of seconds simulated
sim_ticks 362428997000 # Number of ticks simulated sim_ticks 362481577000 # Number of ticks simulated
final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1801112 # Simulator instruction rate (inst/s) host_inst_rate 1217197 # Simulator instruction rate (inst/s)
host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s) host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2677225778 # Simulator tick rate (ticks/s) host_tick_rate 1809539933 # Simulator tick rate (ticks/s)
host_mem_usage 354292 # Number of bytes of host memory used host_mem_usage 354248 # Number of bytes of host memory used
host_seconds 135.37 # Real time elapsed on the host host_seconds 200.32 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 56256 # Nu
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724857994 # number of cpu cycles simulated system.cpu.numCycles 724963154 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed system.cpu.committedInsts 243825163 # Number of instructions committed
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 105711442 # nu
system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 724857994 # Number of busy cycles system.cpu.num_busy_cycles 724963154 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits

4
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -532,7 +532,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

9
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:13:04 gem5 started Jul 2 2012 13:12:36
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -21,7 +21,8 @@ new implicit arcs : 23867
active arcs : 25772 active arcs : 25772
simplex iterations : 2663 simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
info: Increasing stack size by one page.
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 66545720000 because target called exit() info: Increasing stack size by one page.
info: Increasing stack size by one page.
Exiting @ tick 68340167000 because target called exit()

1100
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -169,7 +169,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -201,7 +201,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

6
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:17:22 gem5 started Jul 2 2012 13:28:56
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 368062166000 because target called exit() Exiting @ tick 368209254000 because target called exit()

182
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.368062 # Number of seconds simulated sim_seconds 0.368209 # Number of seconds simulated
sim_ticks 368062166000 # Number of ticks simulated sim_ticks 368209254000 # Number of ticks simulated
final_tick 368062166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 915530 # Simulator instruction rate (inst/s) host_inst_rate 606195 # Simulator instruction rate (inst/s)
host_op_rate 1612102 # Simulator op (including micro ops) rate (op/s) host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2132888263 # Simulator tick rate (ticks/s) host_tick_rate 1412802854 # Simulator tick rate (ticks/s)
host_mem_usage 362628 # Number of bytes of host memory used host_mem_usage 363612 # Number of bytes of host memory used
host_seconds 172.57 # Real time elapsed on the host host_seconds 260.62 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 29370 # Nu
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 140498 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5106963 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5247461 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 140498 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 140498 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 39472 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 39472 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 39472 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 140498 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5106963 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5286933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 736124332 # number of cpu cycles simulated system.cpu.numCycles 736418508 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed system.cpu.committedInsts 157988583 # Number of instructions committed
@ -54,16 +54,16 @@ system.cpu.num_mem_refs 122219139 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 736124332 # Number of busy cycles system.cpu.num_busy_cycles 736418508 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 665.896557 # Cycle average of tags in use system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 665.896557 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 42912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 42912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.559519 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 126234114000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.559519 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4076.463091 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995254 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995254 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27464486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 27464486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 27487330000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2704691000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2704691000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 30169177000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 30169177000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30169177000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30169177000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14596.842313 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14596.842313 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21605170000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 21605170000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386362500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2390019500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386362500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2390019500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968688500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23995189500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23968688500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 23995189500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968688500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23995189500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23968688500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 23995189500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.727544 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.727544 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1081 # number of replacements system.cpu.l2cache.replacements 1081 # number of replacements
system.cpu.l2cache.tagsinuse 19721.209952 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 19722.096664 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19369.116114 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 19370.042647 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 209.759091 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 209.723692 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 142.334747 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 142.330324 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.591099 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.006401 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.601844 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.601871 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits

4
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -497,7 +497,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -529,7 +529,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

1
tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

6
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:45:14 gem5 started Jul 2 2012 15:42:24
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 210036334500 because target called exit() Exiting @ tick 213265939500 because target called exit()

1150
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -166,7 +166,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -198,7 +198,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:48:24 gem5 started Jul 2 2012 15:48:14
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 718982756000 because target called exit() Exiting @ tick 720345914000 because target called exit()

190
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.718983 # Number of seconds simulated sim_seconds 0.720346 # Number of seconds simulated
sim_ticks 718982756000 # Number of ticks simulated sim_ticks 720345914000 # Number of ticks simulated
final_tick 718982756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1474104 # Simulator instruction rate (inst/s) host_inst_rate 808443 # Simulator instruction rate (inst/s)
host_op_rate 1661066 # Simulator op (including micro ops) rate (op/s) host_op_rate 910979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2098778351 # Simulator tick rate (ticks/s) host_tick_rate 1153216038 # Simulator tick rate (ticks/s)
host_mem_usage 237008 # Number of bytes of host memory used host_mem_usage 236932 # Number of bytes of host memory used
host_seconds 342.57 # Real time elapsed on the host host_seconds 624.64 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated sim_ops 569034839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 150998 # Nu
system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory
system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 248084 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 247614 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13441034 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 13415599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13689118 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13663213 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 248084 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 247614 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 248084 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 247614 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 9144475 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 9127171 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 9144475 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 9127171 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 9144475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 9127171 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 248084 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 247614 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13441034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 13415599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 22833594 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 22790384 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1437965512 # number of cpu cycles simulated system.cpu.numCycles 1440691828 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 504986853 # Number of instructions committed system.cpu.committedInsts 504986853 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu
system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_load_insts 126029555 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1437965512 # Number of busy cycles system.cpu.num_busy_cycles 1440691828 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 9788 # number of replacements system.cpu.icache.replacements 9788 # number of replacements
system.cpu.icache.tagsinuse 983.088334 # Cycle average of tags in use system.cpu.icache.tagsinuse 983.378720 # Cycle average of tags in use
system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 983.088334 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 983.378720 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.480024 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.480165 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.480024 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.480165 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
system.cpu.icache.overall_misses::total 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 278348000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 279753000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 278348000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 279753000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 278348000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 279753000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 278348000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 279753000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 278348000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 279753000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 278348000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 279753000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24160.055551 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 24282.006770 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24160.055551 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 24282.006770 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243785000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 245190000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 243785000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 245190000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243785000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 245190000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 243785000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 245190000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243785000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 245190000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 243785000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 245190000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1134822 # number of replacements system.cpu.dcache.replacements 1134822 # number of replacements
system.cpu.dcache.tagsinuse 4065.352134 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4065.381389 # Cycle average of tags in use
system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 11889977000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 11899663000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4065.352134 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4065.381389 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.992518 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.992525 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.992518 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.992525 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12960486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 13181704000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12960486000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 13181704000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9326282000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327564000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9326282000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9327564000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22286768000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 22509268000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22286768000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 22509268000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22286768000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 22509268000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22286768000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 22509268000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19568.369277 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 19763.730137 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19568.369277 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 19763.730137 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10612512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10833730000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10612512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10833730000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257502000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8258784000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257502000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8258784000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870014000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19092514000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 18870014000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 19092514000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870014000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19092514000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 18870014000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 19092514000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 122482 # number of replacements system.cpu.l2cache.replacements 122482 # number of replacements
system.cpu.l2cache.tagsinuse 26935.750905 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 26939.836590 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 344124821000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 344531371000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 23223.605882 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 23226.765026 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 246.683502 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 246.719769 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 3465.461521 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 3466.351794 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.708728 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.708825 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007528 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.007529 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.105757 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.105785 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.822014 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.822139 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits

4
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -532,7 +532,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

10
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,15 +1,15 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:20:26 gem5 started Jul 2 2012 13:33:28
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: ***********************info: Increasing stack size by one page. Reading the dictionary files: ***********************info: Increasing stack size by one page.
********************info: Increasing stack size by one page. ***************info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
@ -22,7 +22,7 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
****** ***********
58924 words stored in 3784810 bytes 58924 words stored in 3784810 bytes
@ -80,4 +80,4 @@ Echoing of input sentence turned on.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 455813328500 because target called exit() Exiting @ tick 460577560500 because target called exit()

1142
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -169,7 +169,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -201,7 +201,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master

6
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:08:09 gem5 compiled Jul 2 2012 08:58:39
gem5 started Jun 28 2012 23:33:45 gem5 started Jul 2 2012 13:47:25
gem5 executing on zizzer gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -69,4 +69,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 1652422044000 because target called exit() Exiting @ tick 1652606875000 because target called exit()

188
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 1.652422 # Number of seconds simulated sim_seconds 1.652607 # Number of seconds simulated
sim_ticks 1652422044000 # Number of ticks simulated sim_ticks 1652606875000 # Number of ticks simulated
final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1001096 # Simulator instruction rate (inst/s) host_inst_rate 673883 # Simulator instruction rate (inst/s)
host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s) host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2000579398 # Simulator tick rate (ticks/s) host_tick_rate 1346830511 # Simulator tick rate (ticks/s)
host_mem_usage 231692 # Number of bytes of host memory used host_mem_usage 232676 # Number of bytes of host memory used
host_seconds 825.97 # Real time elapsed on the host host_seconds 1227.03 # Real time elapsed on the host
sim_insts 826877145 # Number of instructions simulated sim_insts 826877145 # Number of instructions simulated
sim_ops 1528988757 # Number of ops (including micro ops) simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 427498 # Nu
system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3304844088 # number of cpu cycles simulated system.cpu.numCycles 3305213750 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877145 # Number of instructions committed system.cpu.committedInsts 826877145 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262345 # nu
system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3304844088 # Number of busy cycles system.cpu.num_busy_cycles 3305213750 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 403150 # number of replacements system.cpu.l2cache.replacements 403150 # number of replacements
system.cpu.l2cache.tagsinuse 29113.171325 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 772998682000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21035.686564 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 79.698096 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 7997.786666 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641958 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.244073 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.888463 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits

4
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -181,7 +181,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -213,7 +213,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:10:46 gem5 started Jul 2 2012 09:12:34
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -11,4 +11,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1 Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.133333 OO-style eon Time= 0.133333
Exiting @ tick 141174877500 because target called exit() Exiting @ tick 141187061500 because target called exit()

564
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.141175 # Number of seconds simulated sim_seconds 0.141187 # Number of seconds simulated
sim_ticks 141174877500 # Number of ticks simulated sim_ticks 141187061500 # Number of ticks simulated
final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 141187061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 165783 # Simulator instruction rate (inst/s) host_inst_rate 158597 # Simulator instruction rate (inst/s)
host_op_rate 165783 # Simulator op (including micro ops) rate (op/s) host_op_rate 158597 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58706881 # Simulator tick rate (ticks/s) host_tick_rate 56167220 # Simulator tick rate (ticks/s)
host_mem_usage 225068 # Number of bytes of host memory used host_mem_usage 225028 # Number of bytes of host memory used
host_seconds 2404.74 # Real time elapsed on the host host_seconds 2513.69 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 214592 # Nu
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1519913 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1799145 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3319058 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1519913 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1519913 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1519913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1799145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3319058 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94755013 # DTB read hits system.cpu.dtb.read_hits 94755019 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94755034 # DTB read accesses system.cpu.dtb.read_accesses 94755040 # DTB read accesses
system.cpu.dtb.write_hits 73522045 # DTB write hits system.cpu.dtb.write_hits 73522100 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73522080 # DTB write accesses system.cpu.dtb.write_accesses 73522135 # DTB write accesses
system.cpu.dtb.data_hits 168277058 # DTB hits system.cpu.dtb.data_hits 168277119 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277114 # DTB accesses system.cpu.dtb.data_accesses 168277175 # DTB accesses
system.cpu.itb.fetch_hits 49111850 # ITB hits system.cpu.itb.fetch_hits 49112134 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_misses 88783 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 49200632 # ITB accesses system.cpu.itb.fetch_accesses 49200917 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 282349756 # number of cpu cycles simulated system.cpu.numCycles 282374124 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups system.cpu.branch_predictor.lookups 53870034 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 30921446 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 16037248 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 33426490 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.BTBHits 15653868 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 46.830726 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 29683710 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 24186324 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 280818505 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 440154364 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 119907678 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 220104159 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 100457715 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations system.cpu.agen_unit.agens 168700471 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 14475138 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 1561451 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 16036589 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 28550962 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 35.966517 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. system.cpu.execution_unit.executions 205751085 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 2124334 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 281932231 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 9236 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 13499283 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. system.cpu.runCycles 268874841 # Number of cycles cpu stages are processed.
system.cpu.activity 95.227384 # Percentage of cycles cpu is active system.cpu.activity 95.219363 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -107,72 +107,72 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.708300 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.708300 # CPI: Total CPI of All Threads
system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.411831 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.411831 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 78560366 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 203813758 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 72.178624 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 108887705 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 173486419 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 61.438497 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 104664774 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 177709350 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 62.934007 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 183592728 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 98781396 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 34.982453 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 92681683 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 189692441 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 67.177700 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements system.cpu.icache.replacements 1973 # number of replacements
system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use system.cpu.icache.tagsinuse 1829.856986 # Cycle average of tags in use
system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. system.cpu.icache.total_refs 49107743 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 3900 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.avg_refs 12591.728974 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1829.856986 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.893485 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.893485 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 49107743 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 49107743 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 49107743 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 49107743 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 49107743 # number of overall hits
system.cpu.icache.overall_hits::total 49107469 # number of overall hits system.cpu.icache.overall_hits::total 49107743 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 4390 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4390 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 4390 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4390 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 4390 # number of overall misses
system.cpu.icache.overall_misses::total 4380 # number of overall misses system.cpu.icache.overall_misses::total 4390 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 220305000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 220305000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 220305000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 220305000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 220305000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 220305000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 49112133 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 49112133 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 49112133 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 49112133 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 49112133 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 49112133 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 50183.371298 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 50183.371298 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 490 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 490 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 490 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 490 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 490 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3900 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3900 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3900 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3900 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3900 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3900 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190927000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 190927000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190927000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 190927000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190927000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 190927000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3284.708505 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.total_refs 168261813 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 40525.484827 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3284.708505 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.801931 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.801931 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73508552 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73508552 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 168261813 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168261813 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 168261813 # number of overall hits
system.cpu.dcache.overall_hits::total 168261959 # number of overall hits system.cpu.dcache.overall_hits::total 168261813 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 12177 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 12177 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 13405 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 13405 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 13405 # number of overall misses
system.cpu.dcache.overall_misses::total 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13405 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 68612500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 68612500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 712613500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 712613500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 781226000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 781226000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 781226000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 781226000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 58278.701977 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 58278.701977 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 86009500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1905 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8975 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 8975 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9107 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 9253 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9107 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 9253 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9107 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 9253 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9107 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 9253 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48743500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 48743500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 176149500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 176149500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224893000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 224893000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224893000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 224893000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3900.249221 # Cycle average of tags in use
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.159839 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 370.495467 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2902.223601 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 627.530153 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.088569 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.119026 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 547 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 670 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 547 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 730 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 547 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.overall_hits::total 730 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses
@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 7322 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180755000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45853500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 226608500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 171775500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 171775500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 180755000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 217629000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 398384000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 180755000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 217629000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 398384000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 3900 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4847 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 3900 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 8052 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 3900 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 8052 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859744 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.861770 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859744 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.909339 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859744 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909339 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 7322
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139951500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35886500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175838000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133424000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133424000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139951500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169310500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 309262000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139951500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169310500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 309262000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861770 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.909339 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909339 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

4
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -479,7 +479,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -511,7 +511,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:10:52 gem5 started Jul 2 2012 09:15:17
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -11,4 +11,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1 Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.066667 OO-style eon Time= 0.066667
Exiting @ tick 80278875500 because target called exit() Exiting @ tick 80362284000 because target called exit()

1024
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

4
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -148,7 +148,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -180,7 +180,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:12:10 gem5 started Jul 2 2012 09:39:35
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -11,4 +11,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1 Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.566667 OO-style eon Time= 0.566667
Exiting @ tick 567342918000 because target called exit() Exiting @ tick 567365869000 because target called exit()

176
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.567343 # Number of seconds simulated sim_seconds 0.567366 # Number of seconds simulated
sim_ticks 567342918000 # Number of ticks simulated sim_ticks 567365869000 # Number of ticks simulated
final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 567365869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2055836 # Simulator instruction rate (inst/s) host_inst_rate 2066411 # Simulator instruction rate (inst/s)
host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s) host_op_rate 2066411 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2925676505 # Simulator tick rate (ticks/s) host_tick_rate 2940844836 # Simulator tick rate (ticks/s)
host_mem_usage 224040 # Number of bytes of host memory used host_mem_usage 224004 # Number of bytes of host memory used
host_seconds 193.92 # Real time elapsed on the host host_seconds 192.93 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 361530 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 447711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 809241 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 361530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 361530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 361530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809241 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 1134685836 # number of cpu cycles simulated system.cpu.numCycles 1134731738 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664609 # Number of instructions committed system.cpu.committedInsts 398664609 # Number of instructions committed
@ -79,18 +79,18 @@ system.cpu.num_mem_refs 168275276 # nu
system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1134685836 # Number of busy cycles system.cpu.num_busy_cycles 1134731738 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use system.cpu.icache.tagsinuse 1795.107538 # Cycle average of tags in use
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1795.107538 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.876517 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.876517 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
system.cpu.icache.overall_misses::total 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 186108000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 186108000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 186108000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 186108000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 186108000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 186108000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 50669.207732 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 50669.207732 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175089000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 175089000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175089000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 175089000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175089000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 175089000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3288.859436 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3288.859436 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.802944 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.802944 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
system.cpu.dcache.overall_misses::total 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 48094000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 48094000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 176797000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 176797000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 224891000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 224891000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 224891000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 224891000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 54164.499037 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 54164.499037 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 45244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167191000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 167191000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212435000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 212435000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212435000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 212435000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3772.396394 # Cycle average of tags in use
system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 371.526936 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2770.408528 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 630.460931 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.084546 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.115124 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits

4
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -497,7 +497,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -529,7 +529,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:48:53 gem5 started Jul 2 2012 15:48:29
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.070000 OO-style eon Time= 0.070000
Exiting @ tick 71244143500 because target called exit() Exiting @ tick 71229334000 because target called exit()

1040
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
View file

@ -166,7 +166,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -198,7 +198,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14 gem5 compiled Jul 2 2012 09:08:16
gem5 started Jun 29 2012 00:56:30 gem5 started Jul 2 2012 16:02:17
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.520000 OO-style eon Time= 0.520000
Exiting @ tick 525854423000 because target called exit() Exiting @ tick 525920061000 because target called exit()

176
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.525854 # Number of seconds simulated sim_seconds 0.525920 # Number of seconds simulated
sim_ticks 525854423000 # Number of ticks simulated sim_ticks 525920061000 # Number of ticks simulated
final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1009014 # Simulator instruction rate (inst/s) host_inst_rate 966127 # Simulator instruction rate (inst/s)
host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) host_op_rate 1235157 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1945426950 # Simulator tick rate (ticks/s) host_tick_rate 1862970627 # Simulator tick rate (ticks/s)
host_mem_usage 241152 # Number of bytes of host memory used host_mem_usage 241076 # Number of bytes of host memory used
host_seconds 270.30 # Real time elapsed on the host host_seconds 282.30 # Real time elapsed on the host
sim_insts 272739283 # Number of instructions simulated sim_insts 272739283 # Number of instructions simulated
sim_ops 348687122 # Number of ops (including micro ops) simulated sim_ops 348687122 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 166976 # Nu
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1051708846 # number of cpu cycles simulated system.cpu.numCycles 1051840122 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272739283 # Number of instructions committed system.cpu.committedInsts 272739283 # Number of instructions committed
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 177024356 # nu
system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_load_insts 94648757 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1051708846 # Number of busy cycles system.cpu.num_busy_cycles 1051840122 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 13796 # number of replacements system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use
system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1332 # number of replacements system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use
system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 4478 # n
system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
system.cpu.dcache.overall_misses::total 4478 # number of overall misses system.cpu.dcache.overall_misses::total 4478 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4478
system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits

4
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -479,7 +479,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -511,7 +511,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:12:31 gem5 started Jul 2 2012 09:41:27
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391 2000: 760651391
1000: 4031656975 1000: 4031656975
0: 2206428413 0: 2206428413
Exiting @ tick 639588907000 because target called exit() Exiting @ tick 646278131000 because target called exit()

1132
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -148,7 +148,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -180,7 +180,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

6
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18 gem5 compiled Jul 2 2012 08:30:56
gem5 started Jun 28 2012 22:15:06 gem5 started Jul 2 2012 09:50:30
gem5 executing on zizzer gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391 2000: 760651391
1000: 4031656975 1000: 4031656975
0: 2206428413 0: 2206428413
Exiting @ tick 2813377164000 because target called exit() Exiting @ tick 2813572242000 because target called exit()

186
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 2.813377 # Number of seconds simulated sim_seconds 2.813572 # Number of seconds simulated
sim_ticks 2813377164000 # Number of ticks simulated sim_ticks 2813572242000 # Number of ticks simulated
final_tick 2813377164000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2127881 # Simulator instruction rate (inst/s) host_inst_rate 1893151 # Simulator instruction rate (inst/s)
host_op_rate 2127880 # Simulator op (including micro ops) rate (op/s) host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2979874149 # Simulator tick rate (ticks/s) host_tick_rate 2651343461 # Simulator tick rate (ticks/s)
host_mem_usage 227924 # Number of bytes of host memory used host_mem_usage 227888 # Number of bytes of host memory used
host_seconds 944.13 # Real time elapsed on the host host_seconds 1061.19 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu
system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54073 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 33560326 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 33614400 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54073 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54073 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1521827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1521827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1521827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 33560326 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35136226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 5626754328 # number of cpu cycles simulated system.cpu.numCycles 5627144484 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2008987605 # Number of instructions committed system.cpu.committedInsts 2008987605 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu
system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_load_insts 511488910 # Number of load instructions
system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_store_insts 210809477 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5626754328 # Number of busy cycles system.cpu.num_busy_cycles 5627144484 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.tagsinuse 1478.423352 # Cycle average of tags in use system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1478.423352 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n
system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
system.cpu.icache.overall_misses::total 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 248178000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 248178000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 248178000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 248178000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 248178000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 248178000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23421.857305 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596
system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.tagsinuse 4095.204600 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.204600 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n
system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
system.cpu.dcache.overall_misses::total 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567740000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 79567740000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3815994000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3815994000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 83383734000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 83383734000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 83383734000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 83383734000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120
system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.024227 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.024227 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54494.043698 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54494.043698 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144
system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120
system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1479705 # number of replacements system.cpu.l2cache.replacements 1479705 # number of replacements
system.cpu.l2cache.tagsinuse 32704.227313 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use
system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 3254.893374 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 33.487953 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 29415.845986 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.099331 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.897700 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.998054 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits

4
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -497,7 +497,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -529,7 +529,7 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side

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