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arm: Bump stats after FS config script update

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This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
This commit is contained in:
Andreas Hansson 2014-02-19 07:59:46 -05:00
parent 6b765ba8b7
commit fd9343eb85
11 changed files with 12534 additions and 12557 deletions
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2948
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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4215
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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2926
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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3198
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
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3622
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
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2046
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
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466
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
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@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.912097 # Number of seconds simulated
sim_ticks 912096767500 # Number of ticks simulated
final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.912098 # Number of seconds simulated
sim_ticks 912098398000 # Number of ticks simulated
final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 734225 # Simulator instruction rate (inst/s)
host_op_rate 945306 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10865482551 # Simulator tick rate (ticks/s)
host_mem_usage 476960 # Number of bytes of host memory used
host_seconds 83.94 # Real time elapsed on the host
sim_insts 61634065 # Number of instructions simulated
sim_ops 79353129 # Number of ops (including micro ops) simulated
host_inst_rate 1169212 # Simulator instruction rate (inst/s)
host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17301899059 # Simulator tick rate (ticks/s)
host_mem_usage 421332 # Number of bytes of host memory used
host_seconds 52.72 # Real time elapsed on the host
sim_insts 61636937 # Number of instructions simulated
sim_ops 79356422 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
@ -35,76 +35,76 @@ system.physmem.bytes_read::realview.clcd 39321600 # Nu
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory
system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 64986682 # Throughput (bytes/s)
system.membus.data_through_bus 59274143 # Total data (bytes)
system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 64987015 # Throughput (bytes/s)
system.membus.data_through_bus 59274552 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 70658 # number of replacements
system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use
system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks.
system.l2c.tags.replacements 70660 # number of replacements
system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use
system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
@ -112,7 +112,7 @@ system.l2c.tags.occ_percent::cpu0.data 0.037879 # Av
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
@ -124,46 +124,46 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 #
system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 16908094 # Number of tag accesses
system.l2c.tags.data_accesses 16908094 # Number of data accesses
system.l2c.tags.tag_accesses 16908072 # Number of tag accesses
system.l2c.tags.data_accesses 16908072 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits
system.l2c.Writeback_hits::total 567807 # number of Writeback hits
system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits
system.l2c.Writeback_hits::total 567806 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits
system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
system.l2c.overall_hits::cpu0.data 233336 # number of overall hits
system.l2c.overall_hits::cpu0.data 233332 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
system.l2c.overall_hits::total 1317466 # number of overall hits
system.l2c.overall_hits::total 1317462 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
@ -178,63 +178,63 @@ system.l2c.UpgradeReq_misses::total 9391 # nu
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
system.l2c.demand_misses::total 163290 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses
system.l2c.demand_misses::total 163292 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
system.l2c.overall_misses::cpu0.data 98856 # number of overall misses
system.l2c.overall_misses::cpu0.data 98857 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
system.l2c.overall_misses::total 163290 # number of overall misses
system.l2c.overall_misses::cpu1.data 53649 # number of overall misses
system.l2c.overall_misses::total 163292 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
@ -249,25 +249,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.880544 # mi
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -276,8 +276,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 65559 # number of writebacks
system.l2c.writebacks::total 65559 # number of writebacks
system.l2c.writebacks::writebacks 65561 # number of writebacks
system.l2c.writebacks::total 65561 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -285,11 +285,11 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 154019994 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 140481139 # Total data (bytes)
system.toL2Bus.throughput 154019817 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 140481228 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iobus.throughput 45730949 # Throughput (bytes/s)
system.iobus.data_through_bus 41711051 # Total data (bytes)
system.iobus.throughput 45731035 # Throughput (bytes/s)
system.iobus.data_through_bus 41711204 # Total data (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -313,9 +313,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7977216 # DTB read hits
system.cpu0.dtb.read_hits 7977762 # DTB read hits
system.cpu0.dtb.read_misses 3611 # DTB read misses
system.cpu0.dtb.write_hits 5966960 # DTB write hits
system.cpu0.dtb.write_hits 5967140 # DTB write hits
system.cpu0.dtb.write_misses 672 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
@ -326,12 +326,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7980827 # DTB read accesses
system.cpu0.dtb.write_accesses 5967632 # DTB write accesses
system.cpu0.dtb.read_accesses 7981373 # DTB read accesses
system.cpu0.dtb.write_accesses 5967812 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 13944176 # DTB hits
system.cpu0.dtb.hits 13944902 # DTB hits
system.cpu0.dtb.misses 4283 # DTB misses
system.cpu0.dtb.accesses 13948459 # DTB accesses
system.cpu0.dtb.accesses 13949185 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -353,7 +353,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 30245736 # ITB inst hits
system.cpu0.itb.inst_hits 30248608 # ITB inst hits
system.cpu0.itb.inst_misses 2175 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@ -370,74 +370,74 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses
system.cpu0.itb.hits 30245736 # DTB hits
system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses
system.cpu0.itb.hits 30248608 # DTB hits
system.cpu0.itb.misses 2175 # DTB misses
system.cpu0.itb.accesses 30247911 # DTB accesses
system.cpu0.numCycles 1823671415 # number of cpu cycles simulated
system.cpu0.itb.accesses 30250783 # DTB accesses
system.cpu0.numCycles 1823674676 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 29756754 # Number of instructions committed
system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses
system.cpu0.committedInsts 29759626 # Number of instructions committed
system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
system.cpu0.num_func_calls 1242676 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34752271 # number of integer instructions
system.cpu0.num_func_calls 1242746 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34755088 # number of integer instructions
system.cpu0.num_fp_insts 5449 # number of float instructions
system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written
system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
system.cpu0.num_mem_refs 14629077 # number of memory refs
system.cpu0.num_load_insts 8358676 # Number of load instructions
system.cpu0.num_store_insts 6270401 # Number of store instructions
system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles
system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles
system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles
system.cpu0.Branches 5491598 # Number of branches fetched
system.cpu0.num_mem_refs 14629859 # number of memory refs
system.cpu0.num_load_insts 8359235 # Number of load instructions
system.cpu0.num_store_insts 6270624 # Number of store instructions
system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles
system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles
system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles
system.cpu0.Branches 5492144 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 428546 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks.
system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits
system.cpu0.icache.overall_hits::total 29818047 # number of overall hits
system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits
system.cpu0.icache.overall_hits::total 29820919 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
system.cpu0.icache.overall_misses::total 429059 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -447,68 +447,68 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 323609 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks.
system.cpu0.dcache.tags.replacements 323608 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits
system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits
system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits
system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits
system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses
system.cpu0.dcache.overall_misses::total 364518 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses
system.cpu0.dcache.overall_misses::total 364517 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -517,8 +517,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks
system.cpu0.dcache.writebacks::total 300958 # number of writebacks
system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks
system.cpu0.dcache.writebacks::total 300957 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
@ -604,7 +604,7 @@ system.cpu1.itb.inst_accesses 32415891 # IT
system.cpu1.itb.hits 32413691 # DTB hits
system.cpu1.itb.misses 2200 # DTB misses
system.cpu1.itb.accesses 32415891 # DTB accesses
system.cpu1.numCycles 1824193536 # number of cpu cycles simulated
system.cpu1.numCycles 1824196797 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 31877311 # Number of instructions committed
@ -622,7 +622,7 @@ system.cpu1.num_fp_register_writes 1416 # nu
system.cpu1.num_mem_refs 13371151 # number of memory refs
system.cpu1.num_load_insts 7642991 # Number of load instructions
system.cpu1.num_store_insts 5728160 # Number of store instructions
system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles
system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles
system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles
system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
@ -630,14 +630,14 @@ system.cpu1.Branches 5037975 # Nu
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
system.cpu1.icache.tags.replacements 433942 # number of replacements
system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use
system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy
system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
@ -680,46 +680,46 @@ system.cpu1.icache.fast_writes 0 # nu
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 294289 # number of replacements
system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks.
system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy
system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits
system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits
system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses
system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits
system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses
system.cpu1.dcache.overall_misses::total 324341 # number of overall misses
system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses
system.cpu1.dcache.overall_misses::total 324342 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses)
@ -734,8 +734,8 @@ system.cpu1.dcache.overall_accesses::cpu1.data 11847109
system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses

332
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.332810 # Number of seconds simulated
sim_ticks 2332810269000 # Number of ticks simulated
final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.332812 # Number of seconds simulated
sim_ticks 2332811899500 # Number of ticks simulated
final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 702757 # Simulator instruction rate (inst/s)
host_op_rate 903702 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27138460197 # Simulator tick rate (ticks/s)
host_mem_usage 475940 # Number of bytes of host memory used
host_seconds 85.96 # Real time elapsed on the host
sim_insts 60408649 # Number of instructions simulated
sim_ops 77681829 # Number of ops (including micro ops) simulated
host_inst_rate 1065837 # Simulator instruction rate (inst/s)
host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41157671581 # Simulator tick rate (ticks/s)
host_mem_usage 420236 # Number of bytes of host memory used
host_seconds 56.68 # Real time elapsed on the host
sim_insts 60411489 # Number of instructions simulated
sim_ops 77685090 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
@ -29,42 +29,42 @@ system.physmem.bytes_read::realview.clcd 111673344 # Nu
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55969605 # Throughput (bytes/s)
system.membus.data_through_bus 130566470 # Total data (bytes)
system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55969769 # Throughput (bytes/s)
system.membus.data_through_bus 130566943 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.iobus.throughput 48895252 # Throughput (bytes/s)
system.iobus.data_through_bus 114063346 # Total data (bytes)
system.iobus.throughput 48895283 # Throughput (bytes/s)
system.iobus.data_through_bus 114063499 # Total data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
@ -98,9 +98,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14971217 # DTB read hits
system.cpu.dtb.read_hits 14971763 # DTB read hits
system.cpu.dtb.read_misses 7294 # DTB read misses
system.cpu.dtb.write_hits 11217004 # DTB write hits
system.cpu.dtb.write_hits 11217184 # DTB write hits
system.cpu.dtb.write_misses 2181 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
@ -111,12 +111,12 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 14978511 # DTB read accesses
system.cpu.dtb.write_accesses 11219185 # DTB write accesses
system.cpu.dtb.read_accesses 14979057 # DTB read accesses
system.cpu.dtb.write_accesses 11219365 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26188221 # DTB hits
system.cpu.dtb.hits 26188947 # DTB hits
system.cpu.dtb.misses 9475 # DTB misses
system.cpu.dtb.accesses 26197696 # DTB accesses
system.cpu.dtb.accesses 26198422 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 61431840 # ITB inst hits
system.cpu.itb.inst_hits 61434680 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@ -155,42 +155,42 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
system.cpu.itb.hits 61431840 # DTB hits
system.cpu.itb.inst_accesses 61439151 # ITB inst accesses
system.cpu.itb.hits 61434680 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61436311 # DTB accesses
system.cpu.numCycles 4665620539 # number of cpu cycles simulated
system.cpu.itb.accesses 61439151 # DTB accesses
system.cpu.numCycles 4665623800 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60408649 # Number of instructions committed
system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses
system.cpu.committedInsts 60411489 # Number of instructions committed
system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2136008 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls
system.cpu.num_int_insts 69130761 # number of integer instructions
system.cpu.num_func_calls 2136078 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls
system.cpu.num_int_insts 69133554 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read
system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written
system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read
system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27361639 # number of memory refs
system.cpu.num_load_insts 15639529 # Number of load instructions
system.cpu.num_store_insts 11722110 # Number of store instructions
system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles
system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles
system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
system.cpu.Branches 10298723 # Number of branches fetched
system.cpu.num_mem_refs 27362421 # number of memory refs
system.cpu.num_load_insts 15640088 # Number of load instructions
system.cpu.num_store_insts 11722333 # Number of store instructions
system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles
system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983110 # Percentage of idle cycles
system.cpu.Branches 10299261 # Number of branches fetched
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 850590 # number of replacements
system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor
system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@ -199,32 +199,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 78
system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses
system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
system.cpu.icache.overall_hits::total 60583498 # number of overall hits
system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses
system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits
system.cpu.icache.overall_hits::total 60586338 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
system.cpu.icache.overall_misses::total 851102 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -234,23 +234,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 62243 # number of replacements
system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
system.cpu.l2cache.tags.replacements 62245 # number of replacements
system.cpu.l2cache.tags.tagsinuse 50007.460447 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1669929 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127630 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 13.084142 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36899.777920 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960146 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.716487 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.011961 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563046 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.763053 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
@ -261,15 +261,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses
system.cpu.l2cache.tags.tag_accesses 17035991 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 17035991 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits::cpu.data 366775 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1216282 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 592648 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 592648 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
@ -277,13 +277,13 @@ system.cpu.l2cache.ReadExReq_hits::total 113739 # nu
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 480514 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1330021 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 480514 # number of overall hits
system.cpu.l2cache.overall_hits::total 1330021 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
@ -291,39 +291,39 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 9871 #
system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133470 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133470 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143341 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153953 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143341 # number of overall misses
system.cpu.l2cache.overall_misses::total 153953 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 376646 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1236765 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 592648 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 592648 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 623855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1483974 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 623855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1483974 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
@ -331,18 +331,18 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208
system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539908 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539908 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103744 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103744 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -351,14 +351,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks
system.cpu.l2cache.writebacks::total 57866 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 623337 # number of replacements
system.cpu.dcache.tags.replacements 623343 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.
system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
@ -368,44 +368,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 278
system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits
system.cpu.dcache.overall_hits::total 23142807 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
system.cpu.dcache.overall_misses::total 615611 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses
system.cpu.dcache.overall_misses::total 615617 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
@ -422,11 +422,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
system.cpu.dcache.writebacks::total 592643 # number of writebacks
system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks
system.cpu.dcache.writebacks::total 592648 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes)
system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use

2909
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
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@ -1,69 +1,69 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.332810 # Number of seconds simulated
sim_ticks 2332810269000 # Number of ticks simulated
final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.332812 # Number of seconds simulated
sim_ticks 2332811899500 # Number of ticks simulated
final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1221068 # Simulator instruction rate (inst/s)
host_op_rate 1570218 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47154151043 # Simulator tick rate (ticks/s)
host_mem_usage 421264 # Number of bytes of host memory used
host_seconds 49.47 # Real time elapsed on the host
sim_insts 60408649 # Number of instructions simulated
sim_ops 77681829 # Number of ops (including micro ops) simulated
host_inst_rate 1003640 # Simulator instruction rate (inst/s)
host_op_rate 1290613 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38755909714 # Simulator tick rate (ticks/s)
host_mem_usage 421296 # Number of bytes of host memory used
host_seconds 60.19 # Real time elapsed on the host
sim_insts 60411489 # Number of instructions simulated
sim_ops 77685090 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 492744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6494808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450764 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 492744 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6490328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2581740 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450892 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory
system.physmem.bytes_written::total 6718884 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1610064 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719076 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 13911 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 101517 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118198 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811821 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 101447 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 40350 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118200 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 402516 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811824 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 211223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2784113 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 211223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2782191 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1106707 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52062017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587454 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 690182 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880248 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 211223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3386727 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3384803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1796889 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942264 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
@ -76,31 +76,31 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55969581 # Throughput (bytes/s)
system.membus.data_through_bus 130566414 # Total data (bytes)
system.membus.throughput 55969745 # Throughput (bytes/s)
system.membus.data_through_bus 130566887 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 62242 # number of replacements
system.l2c.tags.tagsinuse 50006.300115 # Cycle average of tags in use
system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36900.571374 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
system.l2c.tags.replacements 62244 # number of replacements
system.l2c.tags.tagsinuse 50006.487761 # Cycle average of tags in use
system.l2c.tags.total_refs 1678458 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127629 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.151071 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36900.766383 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4917.298409 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3152.525305 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2097.421521 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2936.495752 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3149.549186 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.563061 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.048058 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.763038 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
@ -111,132 +111,132 @@ system.l2c.tags.age_task_id_blocks_1024::3 9187 #
system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17104735 # Number of tag accesses
system.l2c.tags.data_accesses 17104735 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 473132 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 196968 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 365739 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 169796 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits
system.l2c.Writeback_hits::total 592682 # number of Writeback hits
system.l2c.tags.tag_accesses 17104555 # Number of tag accesses
system.l2c.tags.data_accesses 17104555 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 196973 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 169795 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1224812 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 592687 # number of Writeback hits
system.l2c.Writeback_hits::total 592687 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 63334 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50404 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu0.data 63344 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50394 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 473132 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 260302 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 365739 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 220200 # number of demand (read+write) hits
system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits
system.l2c.overall_hits::cpu0.inst 473132 # number of overall hits
system.l2c.overall_hits::cpu0.data 260302 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits
system.l2c.overall_hits::cpu1.inst 365739 # number of overall hits
system.l2c.overall_hits::cpu1.data 220200 # number of overall hits
system.l2c.overall_hits::total 1338580 # number of overall hits
system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 260317 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 220189 # number of demand (read+write) hits
system.l2c.demand_hits::total 1338550 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits
system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits
system.l2c.overall_hits::cpu0.data 260317 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits
system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits
system.l2c.overall_hits::cpu1.data 220189 # number of overall hits
system.l2c.overall_hits::total 1338550 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7285 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5807 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3319 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4065 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5804 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1520 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1399 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 96488 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 36984 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133472 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu0.data 96422 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 37052 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133474 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7285 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 102295 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3319 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 41049 # number of demand (read+write) misses
system.l2c.demand_misses::total 153953 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 102226 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses
system.l2c.demand_misses::total 153955 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7285 # number of overall misses
system.l2c.overall_misses::cpu0.data 102295 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3319 # number of overall misses
system.l2c.overall_misses::cpu1.data 41049 # number of overall misses
system.l2c.overall_misses::total 153953 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 480417 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 202775 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 369058 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 173861 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses)
system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses
system.l2c.overall_misses::cpu0.data 102226 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses
system.l2c.overall_misses::cpu1.data 41120 # number of overall misses
system.l2c.overall_misses::total 153955 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 202777 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 173863 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1245293 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 592687 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 592687 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 159822 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 87388 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 480417 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 362597 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 369058 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 261249 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 480417 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 362597 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 369058 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 261249 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses
system.l2c.ReadExReq_accesses::cpu0.data 159766 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 87446 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9010 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3282 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 480346 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 362543 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4855 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 2031 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 369129 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 261309 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1492505 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 362543 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 261309 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1492505 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028623 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.023398 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016447 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.603722 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.423216 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.603520 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.423713 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.539917 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.282118 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.157126 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.281969 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.157362 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.103152 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.282118 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.157126 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.281969 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.157362 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.103152 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 57860 # number of writebacks
system.l2c.writebacks::total 57860 # number of writebacks
system.l2c.writebacks::writebacks 57863 # number of writebacks
system.l2c.writebacks::total 57863 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -254,11 +254,11 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 59119271 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 137914042 # Total data (bytes)
system.toL2Bus.throughput 59119535 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 137914755 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iobus.throughput 48895252 # Throughput (bytes/s)
system.iobus.data_through_bus 114063346 # Total data (bytes)
system.iobus.throughput 48895283 # Throughput (bytes/s)
system.iobus.data_through_bus 114063499 # Total data (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7929199 # DTB read hits
system.cpu0.dtb.read_misses 6444 # DTB read misses
system.cpu0.dtb.write_hits 6437089 # DTB write hits
system.cpu0.dtb.read_hits 7929658 # DTB read hits
system.cpu0.dtb.read_misses 6455 # DTB read misses
system.cpu0.dtb.write_hits 6435419 # DTB write hits
system.cpu0.dtb.write_misses 1929 # DTB write misses
system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5568 # Number of entries that have been flushed from TLB
system.cpu0.dtb.flush_entries 5575 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7935643 # DTB read accesses
system.cpu0.dtb.write_accesses 6439018 # DTB write accesses
system.cpu0.dtb.read_accesses 7936113 # DTB read accesses
system.cpu0.dtb.write_accesses 6437348 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 14366288 # DTB hits
system.cpu0.dtb.misses 8373 # DTB misses
system.cpu0.dtb.accesses 14374661 # DTB accesses
system.cpu0.dtb.hits 14365077 # DTB hits
system.cpu0.dtb.misses 8384 # DTB misses
system.cpu0.dtb.accesses 14373461 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -322,62 +322,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 32543256 # ITB inst hits
system.cpu0.itb.inst_misses 3703 # ITB inst misses
system.cpu0.itb.inst_hits 32541992 # ITB inst hits
system.cpu0.itb.inst_misses 3717 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB
system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 32546959 # ITB inst accesses
system.cpu0.itb.hits 32543256 # DTB hits
system.cpu0.itb.misses 3703 # DTB misses
system.cpu0.itb.accesses 32546959 # DTB accesses
system.cpu0.numCycles 4633654699 # number of cpu cycles simulated
system.cpu0.itb.inst_accesses 32545709 # ITB inst accesses
system.cpu0.itb.hits 32541992 # DTB hits
system.cpu0.itb.misses 3717 # DTB misses
system.cpu0.itb.accesses 32545709 # DTB accesses
system.cpu0.numCycles 4625561989 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 31998107 # Number of instructions committed
system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37244533 # Number of integer alu accesses
system.cpu0.committedInsts 31996828 # Number of instructions committed
system.cpu0.committedOps 41898003 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37241416 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses
system.cpu0.num_func_calls 1207172 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4285554 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37244533 # number of integer instructions
system.cpu0.num_func_calls 1207166 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4285035 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37241416 # number of integer instructions
system.cpu0.num_fp_insts 5364 # number of float instructions
system.cpu0.num_int_register_reads 192529528 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39716026 # number of times the integer registers were written
system.cpu0.num_int_register_reads 192512823 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39713188 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written
system.cpu0.num_mem_refs 15013044 # number of memory refs
system.cpu0.num_load_insts 8304661 # Number of load instructions
system.cpu0.num_store_insts 6708383 # Number of store instructions
system.cpu0.num_idle_cycles 4553702806.473283 # Number of idle cycles
system.cpu0.num_busy_cycles 79951892.526717 # Number of busy cycles
system.cpu0.not_idle_fraction 0.017255 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.982745 # Percentage of idle cycles
system.cpu0.Branches 5613939 # Number of branches fetched
system.cpu0.num_mem_refs 15011832 # number of memory refs
system.cpu0.num_load_insts 8305325 # Number of load instructions
system.cpu0.num_store_insts 6706507 # Number of store instructions
system.cpu0.num_idle_cycles 4549718927.235470 # Number of idle cycles
system.cpu0.num_busy_cycles 75843061.764530 # Number of busy cycles
system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles
system.cpu0.Branches 5613326 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 850590 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
system.cpu0.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60586338 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.509134 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.169458 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868182 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131190 # Average percentage of cache occupancy
system.cpu0.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.500524 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.177938 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868165 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131207 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
@ -385,44 +385,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 78
system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 32064740 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 28518758 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32064740 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 28518758 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32064740 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 28518758 # number of overall hits
system.cpu0.icache.overall_hits::total 60583498 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 481295 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 369807 # number of ReadReq misses
system.cpu0.icache.tags.tag_accesses 62288542 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 62288542 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 32063555 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 28522783 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60586338 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32063555 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 28522783 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60586338 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32063555 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 28522783 # number of overall hits
system.cpu0.icache.overall_hits::total 60586338 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 481227 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 369875 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 481295 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 369807 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu0.inst 481227 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 369875 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 481295 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 369807 # number of overall misses
system.cpu0.icache.overall_misses::cpu0.inst 481227 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 369875 # number of overall misses
system.cpu0.icache.overall_misses::total 851102 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546035 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888565 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32546035 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 28888565 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32546035 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 28888565 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014788 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012801 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014788 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012801 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32544782 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 28892658 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32544782 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 28892658 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32544782 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 28892658 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014787 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012802 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014787 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012802 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014787 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012802 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -432,90 +432,90 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 623334 # number of replacements
system.cpu0.dcache.tags.replacements 623340 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23628286 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.875190 # Average number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 23628946 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 623852 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.875884 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298836 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698194 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291431 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705599 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 97632374 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 97632374 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6995580 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184442 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13180022 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5776847 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4185218 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139292 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96744 # number of LoadLockedReq hits
system.cpu0.dcache.tags.tag_accesses 97635044 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 97635044 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184470 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13180521 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4187066 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9962226 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96697 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145938 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101280 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101232 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12772427 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10369660 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23142087 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12772427 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10369660 # number of overall hits
system.cpu0.dcache.overall_hits::total 23142087 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 196128 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 169325 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 365453 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 161354 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 88801 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses
system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10371536 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23142747 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10371536 # number of overall hits
system.cpu0.dcache.overall_hits::total 23142747 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 169328 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 365457 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250157 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6648 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4535 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 357482 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 258126 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 615608 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 357482 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 258126 # number of overall misses
system.cpu0.dcache.overall_misses::total 615608 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191708 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353767 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13545475 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938201 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274019 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145939 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101280 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 258182 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 615614 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 258182 # number of overall misses
system.cpu0.dcache.overall_misses::total 615614 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353798 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13545978 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275920 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10212383 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101232 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145938 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101280 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101232 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13129909 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 10627786 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23757695 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13129909 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 10627786 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23757695 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027271 # miss rate for ReadReq accesses
system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 10629718 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23758361 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 10629718 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23758361 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045546 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044787 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044798 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.025911 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.025911 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -524,8 +524,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks
system.cpu0.dcache.writebacks::total 592682 # number of writebacks
system.cpu0.dcache.writebacks::writebacks 592687 # number of writebacks
system.cpu0.dcache.writebacks::total 592687 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
@ -550,25 +550,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7038606 # DTB read hits
system.cpu1.dtb.read_misses 4220 # DTB read misses
system.cpu1.dtb.write_hits 4778915 # DTB write hits
system.cpu1.dtb.write_misses 1252 # DTB write misses
system.cpu1.dtb.read_hits 7038699 # DTB read hits
system.cpu1.dtb.read_misses 4194 # DTB read misses
system.cpu1.dtb.write_hits 4780763 # DTB write hits
system.cpu1.dtb.write_misses 1254 # DTB write misses
system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2946 # Number of entries that have been flushed from TLB
system.cpu1.dtb.flush_entries 2928 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch
system.cpu1.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7042826 # DTB read accesses
system.cpu1.dtb.write_accesses 4780167 # DTB write accesses
system.cpu1.dtb.read_accesses 7042893 # DTB read accesses
system.cpu1.dtb.write_accesses 4782017 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 11817521 # DTB hits
system.cpu1.dtb.misses 5472 # DTB misses
system.cpu1.dtb.accesses 11822993 # DTB accesses
system.cpu1.dtb.hits 11819462 # DTB hits
system.cpu1.dtb.misses 5448 # DTB misses
system.cpu1.dtb.accesses 11824910 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@ -590,50 +590,50 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 28886889 # ITB inst hits
system.cpu1.itb.inst_misses 2463 # ITB inst misses
system.cpu1.itb.inst_hits 28890998 # ITB inst hits
system.cpu1.itb.inst_misses 2444 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1658 # Number of entries that have been flushed from TLB
system.cpu1.itb.flush_entries 1642 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 28889352 # ITB inst accesses
system.cpu1.itb.hits 28886889 # DTB hits
system.cpu1.itb.misses 2463 # DTB misses
system.cpu1.itb.accesses 28889352 # DTB accesses
system.cpu1.numCycles 4277971820 # number of cpu cycles simulated
system.cpu1.itb.inst_accesses 28893442 # ITB inst accesses
system.cpu1.itb.hits 28890998 # DTB hits
system.cpu1.itb.misses 2444 # DTB misses
system.cpu1.itb.accesses 28893442 # DTB accesses
system.cpu1.numCycles 4282034895 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 28410542 # Number of instructions committed
system.cpu1.committedOps 35780270 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 31886228 # Number of integer alu accesses
system.cpu1.committedInsts 28414661 # Number of instructions committed
system.cpu1.committedOps 35787087 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 31892138 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses
system.cpu1.num_func_calls 928836 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3656561 # number of instructions that are conditional controls
system.cpu1.num_int_insts 31886228 # number of integer instructions
system.cpu1.num_func_calls 928912 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3657531 # number of instructions that are conditional controls
system.cpu1.num_int_insts 31892138 # number of integer instructions
system.cpu1.num_fp_insts 4905 # number of float instructions
system.cpu1.num_int_register_reads 163367229 # number of times the integer registers were read
system.cpu1.num_int_register_writes 34722740 # number of times the integer registers were written
system.cpu1.num_int_register_reads 163397724 # number of times the integer registers were read
system.cpu1.num_int_register_writes 34729085 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written
system.cpu1.num_mem_refs 12348595 # number of memory refs
system.cpu1.num_load_insts 7334868 # Number of load instructions
system.cpu1.num_store_insts 5013727 # Number of store instructions
system.cpu1.num_idle_cycles 4215699127.014197 # Number of idle cycles
system.cpu1.num_busy_cycles 62272692.985803 # Number of busy cycles
system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles
system.cpu1.Branches 4684784 # Number of branches fetched
system.cpu1.num_mem_refs 12350589 # number of memory refs
system.cpu1.num_load_insts 7334763 # Number of load instructions
system.cpu1.num_store_insts 5015826 # Number of store instructions
system.cpu1.num_idle_cycles 4212351630.069436 # Number of idle cycles
system.cpu1.num_busy_cycles 69683264.930565 # Number of busy cycles
system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles
system.cpu1.Branches 4685935 # Number of branches fetched
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements