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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
Andreas Hansson fd9343eb85 arm: Bump stats after FS config script update 
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
2014-02-19 07:59:46 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.629750 # Number of seconds simulated
sim_ticks 2629749511500 # Number of ticks simulated
final_tick 2629749511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 406352 # Simulator instruction rate (inst/s)
host_op_rate 517075 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17746353667 # Simulator tick rate (ticks/s)
host_mem_usage 422316 # Number of bytes of host memory used
host_seconds 148.19 # Real time elapsed on the host
sim_insts 60215342 # Number of instructions simulated
sim_ops 76622873 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 298760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4637400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 405700 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4423316 # Number of bytes read from this memory
system.physmem.bytes_read::total 134021624 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 298760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 405700 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3690048 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1524460 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1491820 # Number of bytes written to this memory
system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 10880 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 72495 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6355 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 69149 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690914 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57657 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 381115 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 372955 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811727 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47250225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 113608 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1763438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 154273 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1682029 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50963646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 113608 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 154273 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 267881 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1403194 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 579698 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 567286 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2550177 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1403194 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47250225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 113608 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2343136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 154273 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2249315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53513824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15690914 # Number of read requests accepted
system.physmem.writeReqs 811727 # Number of write requests accepted
system.physmem.readBursts 15690914 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 811727 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1004216640 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue
system.physmem.bytesWritten 6837504 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 134021624 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6706328 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 704891 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 980392 # Per bank write bursts
system.physmem.perBankRdBursts::1 980206 # Per bank write bursts
system.physmem.perBankRdBursts::2 980222 # Per bank write bursts
system.physmem.perBankRdBursts::3 980431 # Per bank write bursts
system.physmem.perBankRdBursts::4 986950 # Per bank write bursts
system.physmem.perBankRdBursts::5 980708 # Per bank write bursts
system.physmem.perBankRdBursts::6 980610 # Per bank write bursts
system.physmem.perBankRdBursts::7 980424 # Per bank write bursts
system.physmem.perBankRdBursts::8 980615 # Per bank write bursts
system.physmem.perBankRdBursts::9 980431 # Per bank write bursts
system.physmem.perBankRdBursts::10 979815 # Per bank write bursts
system.physmem.perBankRdBursts::11 979558 # Per bank write bursts
system.physmem.perBankRdBursts::12 980153 # Per bank write bursts
system.physmem.perBankRdBursts::13 980093 # Per bank write bursts
system.physmem.perBankRdBursts::14 980167 # Per bank write bursts
system.physmem.perBankRdBursts::15 980110 # Per bank write bursts
system.physmem.perBankWrBursts::0 6736 # Per bank write bursts
system.physmem.perBankWrBursts::1 6598 # Per bank write bursts
system.physmem.perBankWrBursts::2 6606 # Per bank write bursts
system.physmem.perBankWrBursts::3 6671 # Per bank write bursts
system.physmem.perBankWrBursts::4 6749 # Per bank write bursts
system.physmem.perBankWrBursts::5 7050 # Per bank write bursts
system.physmem.perBankWrBursts::6 7030 # Per bank write bursts
system.physmem.perBankWrBursts::7 6882 # Per bank write bursts
system.physmem.perBankWrBursts::8 6998 # Per bank write bursts
system.physmem.perBankWrBursts::9 6828 # Per bank write bursts
system.physmem.perBankWrBursts::10 6323 # Per bank write bursts
system.physmem.perBankWrBursts::11 6124 # Per bank write bursts
system.physmem.perBankWrBursts::12 6612 # Per bank write bursts
system.physmem.perBankWrBursts::13 6392 # Per bank write bursts
system.physmem.perBankWrBursts::14 6620 # Per bank write bursts
system.physmem.perBankWrBursts::15 6617 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2629745080000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6718 # Read request sizes (log2)
system.physmem.readPktSize::3 15532032 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 152164 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754070 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 57657 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1279103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1122938 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1123139 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3790711 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2702315 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2701600 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2718927 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 52097 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 57127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 20457 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 5035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4919 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4859 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4748 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 90358 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 11189.419509 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 1031.170467 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 16748.902235 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 23468 25.97% 25.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 14751 16.33% 42.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 2914 3.22% 45.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 2094 2.32% 47.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 1353 1.50% 49.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 1190 1.32% 50.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 937 1.04% 51.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 1064 1.18% 52.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 629 0.70% 53.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 518 0.57% 54.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 534 0.59% 54.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 581 0.64% 55.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 314 0.35% 55.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 296 0.33% 56.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 233 0.26% 56.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 596 0.66% 56.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 187 0.21% 57.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 143 0.16% 57.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 114 0.13% 57.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 279 0.31% 57.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 129 0.14% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 2228 2.47% 60.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 121 0.13% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 211 0.23% 60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 45 0.05% 60.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 43 0.05% 60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 36 0.04% 60.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 110 0.12% 61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 48 0.05% 61.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 23 0.03% 61.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 356 0.39% 61.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 15 0.02% 61.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 22 0.02% 61.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 81 0.09% 61.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 26 0.03% 61.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 20 0.02% 61.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 19 0.02% 61.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 26 0.03% 61.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 61 0.07% 61.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 22 0.02% 61.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079 332 0.37% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 20 0.02% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 10 0.01% 62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 9 0.01% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 157 0.17% 62.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 12 0.01% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 18 0.02% 62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 11 0.01% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 18 0.02% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 30 0.03% 62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 133 0.15% 62.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 19 0.02% 63.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 8 0.01% 63.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 8 0.01% 63.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 364 0.40% 63.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167 3 0.00% 63.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 3 0.00% 63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 18 0.02% 63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 73 0.08% 63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 14 0.02% 63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 3 0.00% 63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 77 0.09% 63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 17 0.02% 63.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 5 0.01% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 26 0.03% 63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 15 0.02% 63.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 270 0.30% 64.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255 15 0.02% 64.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319 3 0.00% 64.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 73 0.08% 64.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 165 0.18% 64.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 245 0.27% 64.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 396 0.44% 65.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 186 0.21% 65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 266 0.29% 65.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199 514 0.57% 66.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 66 0.07% 66.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 264 0.29% 67.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 190 0.21% 67.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 395 0.44% 67.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 245 0.27% 68.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 65 0.07% 68.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 270 0.30% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 342 0.38% 69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 321 0.36% 70.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 127 0.14% 70.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 73 0.08% 71.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 65 0.07% 71.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903 2 0.00% 72.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 389 0.43% 72.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 126 0.14% 73.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 69 0.08% 73.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 59 0.07% 73.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 322 0.36% 74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 344 0.38% 75.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 69 0.08% 75.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 72 0.08% 75.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 6 0.01% 75.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 266 0.29% 75.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 246 0.27% 75.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 396 0.44% 76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 186 0.21% 76.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 130 0.14% 77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 512 0.57% 77.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 66 0.07% 77.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 264 0.29% 78.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 185 0.20% 78.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 394 0.44% 79.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 246 0.27% 79.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 65 0.07% 79.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847 2 0.00% 80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 339 0.38% 80.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 133 0.15% 80.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263 1 0.00% 82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 66 0.07% 82.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 71 0.08% 83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 386 0.43% 84.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 126 0.14% 84.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 320 0.35% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 68 0.08% 84.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 132 0.15% 85.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 338 0.37% 86.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37696-37703 2 0.00% 86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 65 0.07% 86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 246 0.27% 87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 394 0.44% 87.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 185 0.20% 87.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 264 0.29% 88.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 67 0.07% 88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 512 0.57% 89.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 129 0.14% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42112-42119 1 0.00% 89.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 186 0.21% 89.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 395 0.44% 90.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 246 0.27% 90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 266 0.29% 91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 6 0.01% 91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 69 0.08% 91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 340 0.38% 91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 129 0.14% 91.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 131 0.14% 92.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 320 0.35% 92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343 58 0.06% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 74 0.08% 92.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 70 0.08% 92.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 320 0.35% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 72 0.08% 93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 142 0.16% 93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 388 0.43% 93.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 73 0.08% 93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647 2 0.00% 93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 5356 5.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90358 # Bytes accessed per row activation
system.physmem.totQLat 377355345750 # Total ticks spent queuing
system.physmem.totMemAccLat 474591583250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 78454425000 # Total ticks spent in databus transfers
system.physmem.totBankLat 18781812500 # Total ticks spent accessing banks
system.physmem.avgQLat 24049.33 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1196.99 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30246.32 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.00 # Data bus utilization in percentage
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing
system.physmem.readRowHits 15616397 # Number of row buffer hits during reads
system.physmem.writeRowHits 90966 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.15 # Row buffer hit rate for writes
system.physmem.avgGap 159352.98 # Average gap between requests
system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54425810 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16743683 # Transaction distribution
system.membus.trans_dist::ReadResp 16743683 # Transaction distribution
system.membus.trans_dist::WriteReq 763441 # Transaction distribution
system.membus.trans_dist::WriteResp 763441 # Transaction distribution
system.membus.trans_dist::Writeback 57657 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 131342 # Transaction distribution
system.membus.trans_dist::ReadExResp 131342 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892593 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4279557 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 35343621 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471696 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 18869990 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 143126246 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 143126246 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1225748500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3758000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 18171669500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4990674222 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 35076241500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 62047 # number of replacements
system.l2c.tags.tagsinuse 51602.841569 # Cycle average of tags in use
system.l2c.tags.total_refs 1699505 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127430 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.336773 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2574813583500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 38208.002352 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000703 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2774.091625 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3066.452073 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4246.643785 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3307.650843 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.583008 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.042329 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.046790 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.064799 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.050471 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.787397 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17278266 # Number of tag accesses
system.l2c.tags.data_accesses 17278266 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9823 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 411412 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 183126 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 10084 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 433138 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 187347 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1242132 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596464 # number of Writeback hits
system.l2c.Writeback_hits::total 596464 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57116 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 57419 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114535 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9823 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu0.data 240242 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.itb.walker 3595 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 433138 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 244766 # number of demand (read+write) hits
system.l2c.demand_hits::total 1356667 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9823 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits
system.l2c.overall_hits::cpu0.inst 411412 # number of overall hits
system.l2c.overall_hits::cpu0.data 240242 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 10084 # number of overall hits
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system.l2c.overall_hits::cpu1.inst 433138 # number of overall hits
system.l2c.overall_hits::cpu1.data 244766 # number of overall hits
system.l2c.overall_hits::total 1356667 # number of overall hits
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system.l2c.UpgradeReq_misses::cpu0.data 1344 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1536 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2880 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 67932 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 132978 # number of ReadExReq misses
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system.l2c.overall_misses::cpu1.inst 6338 # number of overall misses
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system.l2c.overall_misses::total 153800 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 304771500 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::cpu1.data 374309250 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu0.data 232990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 231990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 464980 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4846991473 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu1.inst 451834250 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu0.dtb.walker 9823 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 1262954 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596464 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596464 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1357 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1549 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2906 # number of UpgradeReq accesses(hits+misses)
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system.l2c.overall_accesses::cpu0.itb.walker 3609 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1510467 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000554 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu0.data 0.028138 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu1.inst 0.014422 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025615 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990420 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991607 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991053 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu1.data 0.531140 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.537257 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000554 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.010234 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.inst 0.014422 # miss rate for demand accesses
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system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu1.data 76001.878173 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 151.035156 # average UpgradeReq miss latency
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system.l2c.demand_avg_miss_latency::cpu1.inst 71289.720732 # average overall miss latency
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system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6338 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 69971 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153800 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 4254 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 73234 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6338 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 69971 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153800 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250900000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327379750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 371456750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312895750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1262833500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13441344 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15361536 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28802880 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3976712027 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3785150609 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7761862636 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 250900000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4304091777 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 371456750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4098046359 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 9024696136 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 250900000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4304091777 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 371456750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4098046359 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 9024696136 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344358750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83703872750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82981576250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167030650250 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8433139011 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8270681501 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16703820512 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344358750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92137011761 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91252257751 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183734470762 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028138 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025615 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990420 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991607 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991053 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543247 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.531140 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537257 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.222316 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101823 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.222316 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101823 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61746.463599 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63532.131980 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60649.001057 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58539.598819 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58191.904329 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58369.524553 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 52791444 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2472019 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2472019 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 596464 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 247513 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 247513 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725197 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753946 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50584 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7549986 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54755680 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83794182 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79632 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 138658310 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 138658310 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4808748000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3865724000 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4421241528 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 30676250 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48159266 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution
system.iobus.trans_dist::WriteReq 8184 # Transaction distribution
system.iobus.trans_dist::WriteResp 8184 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 126646806 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42583156500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7421730 # DTB read hits
system.cpu0.dtb.read_misses 6821 # DTB read misses
system.cpu0.dtb.write_hits 5623030 # DTB write hits
system.cpu0.dtb.write_misses 1843 # DTB write misses
system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6415 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7428551 # DTB read accesses
system.cpu0.dtb.write_accesses 5624873 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 13044760 # DTB hits
system.cpu0.dtb.misses 8664 # DTB misses
system.cpu0.dtb.accesses 13053424 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 30640130 # ITB inst hits
system.cpu0.itb.inst_misses 3559 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 30643689 # ITB inst accesses
system.cpu0.itb.hits 30640130 # DTB hits
system.cpu0.itb.misses 3559 # DTB misses
system.cpu0.itb.accesses 30643689 # DTB accesses
system.cpu0.numCycles 2628262208 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 30017324 # Number of instructions committed
system.cpu0.committedOps 38175915 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34451316 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses
system.cpu0.num_func_calls 1059150 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3975405 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34451316 # number of integer instructions
system.cpu0.num_fp_insts 4807 # number of float instructions
system.cpu0.num_int_register_reads 199768149 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37153826 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3633 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1176 # number of times the floating registers were written
system.cpu0.num_mem_refs 13618692 # number of memory refs
system.cpu0.num_load_insts 7744625 # Number of load instructions
system.cpu0.num_store_insts 5874067 # Number of store instructions
system.cpu0.num_idle_cycles 2288630899.609074 # Number of idle cycles
system.cpu0.num_busy_cycles 339631308.390926 # Number of busy cycles
system.cpu0.not_idle_fraction 0.129223 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.870777 # Percentage of idle cycles
system.cpu0.Branches 5132509 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 856246 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.851832 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60652701 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 856758 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 70.793271 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 20193023250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.639655 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 292.212178 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.427031 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.570727 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997757 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 62366219 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 62366219 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 30223720 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 30428981 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60652701 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30223720 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 30428981 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60652701 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30223720 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 30428981 # number of overall hits
system.cpu0.icache.overall_hits::total 60652701 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 416410 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 440349 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856759 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 416410 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 440349 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856759 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 416410 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 440349 # number of overall misses
system.cpu0.icache.overall_misses::total 856759 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5686967000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6125458750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11812425750 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5686967000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6125458750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11812425750 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5686967000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6125458750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11812425750 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30640130 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 30869330 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61509460 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30640130 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 30869330 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61509460 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30640130 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 30869330 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61509460 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013590 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014265 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013590 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014265 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013590 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014265 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.133594 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.463632 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13787.337804 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.133594 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.463632 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13787.337804 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.133594 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.463632 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13787.337804 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416410 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440349 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856759 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 416410 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 440349 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856759 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 416410 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 440349 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856759 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852567000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5242306250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10094873250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852567000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5242306250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10094873250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852567000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5242306250 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10094873250 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435943750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435943750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013590 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014265 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013590 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014265 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013590 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014265 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11653.339257 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.889644 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11782.628779 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11653.339257 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.889644 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11782.628779 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11653.339257 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.889644 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11782.628779 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 627701 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.877186 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23661631 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 628213 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.664981 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 664900250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.960449 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 326.916737 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.361251 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638509 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 97787589 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 97787589 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6520468 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6679152 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13199620 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4990639 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4984500 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9975139 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118374 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117820 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236194 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124360 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123412 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247772 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11511107 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 11663652 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23174759 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11511107 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 11663652 # number of overall hits
system.cpu0.dcache.overall_hits::total 23174759 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 182444 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 186677 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 369121 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 126405 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 124014 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250419 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5984 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5595 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11579 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 308849 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 310691 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 619540 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 308849 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 310691 # number of overall misses
system.cpu0.dcache.overall_misses::total 619540 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2722910750 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2758252500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5481163250 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5855218871 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5625941645 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 11481160516 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80735500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79463250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 160198750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8578129621 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 8384194145 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 16962323766 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8578129621 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 8384194145 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 16962323766 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6702912 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6865829 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13568741 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5117044 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5108514 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10225558 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124358 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123415 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124360 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123412 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11819956 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 11974343 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23794299 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11819956 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 11974343 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23794299 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027219 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027189 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024703 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024276 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048119 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045335 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026129 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025946 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026129 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025946 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.026037 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.638519 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14775.534747 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14849.231688 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46321.101784 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45365.375240 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45847.801149 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.895053 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14202.546917 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.283703 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27774.509942 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26985.635712 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 27378.900097 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27774.509942 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26985.635712 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 27378.900097 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 596464 # number of writebacks
system.cpu0.dcache.writebacks::total 596464 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182444 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186677 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 369121 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126405 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 124014 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250419 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5984 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5595 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 308849 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 310691 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 619540 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 308849 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 310691 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619540 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2356704250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2383886500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4740590750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5575941129 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5352926355 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10928867484 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68762500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68225750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136988250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7932645379 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736812855 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 15669458234 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7932645379 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736812855 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 15669458234 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91432491750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647732000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080223750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13248714489 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12991485999 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240200488 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104681206239 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103639217999 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208320424238 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027219 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027189 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024703 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024276 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048119 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045335 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12917.411644 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12770.113619 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12842.918040 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44111.713374 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43163.887585 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43642.325399 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11491.059492 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12194.057194 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.749633 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7578931 # DTB read hits
system.cpu1.dtb.read_misses 7259 # DTB read misses
system.cpu1.dtb.write_hits 5610002 # DTB write hits
system.cpu1.dtb.write_misses 1852 # DTB write misses
system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6696 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7586190 # DTB read accesses
system.cpu1.dtb.write_accesses 5611854 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 13188933 # DTB hits
system.cpu1.dtb.misses 9111 # DTB misses
system.cpu1.dtb.accesses 13198044 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 30869347 # ITB inst hits
system.cpu1.itb.inst_misses 3806 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 30873153 # ITB inst accesses
system.cpu1.itb.hits 30869347 # DTB hits
system.cpu1.itb.misses 3806 # DTB misses
system.cpu1.itb.accesses 30873153 # DTB accesses
system.cpu1.numCycles 2631236815 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 30198018 # Number of instructions committed
system.cpu1.committedOps 38446958 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 34771949 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses
system.cpu1.num_func_calls 1081332 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3974549 # number of instructions that are conditional controls
system.cpu1.num_int_insts 34771949 # number of integer instructions
system.cpu1.num_fp_insts 5462 # number of float instructions
system.cpu1.num_int_register_reads 201690852 # number of times the integer registers were read
system.cpu1.num_int_register_writes 37382680 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written
system.cpu1.num_mem_refs 13782650 # number of memory refs
system.cpu1.num_load_insts 7920272 # Number of load instructions
system.cpu1.num_store_insts 5862378 # Number of store instructions
system.cpu1.num_idle_cycles 2292306354.384825 # Number of idle cycles
system.cpu1.num_busy_cycles 338930460.615175 # Number of busy cycles
system.cpu1.not_idle_fraction 0.128810 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.871190 # Percentage of idle cycles
system.cpu1.Branches 5177848 # Number of branches fetched
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1557250761500 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1557250761500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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